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Study of Ultra Low Power Design and Power Reduction Techniques for VLSI Circuits at Ultra Low Voltages

Varanasi, Phani Kameswara Abhishikth
http://rave.ohiolink.edu/etdc/view?acc_num=ucin1439307481

Abstract Details

2015, MS, University of Cincinnati, Engineering and Applied Science: Computer Engineering.
The advancements and scaling in technology are continuously increasing in accordance with Moore's Law. This results in an increase in the performance of chips, but comes with a price due to the increased power consumption, and hence resources are spent on cooling, packaging and other methods to reduce the after e ffects. This additional cost has to be eliminated, and the most obvious solution is to reduce the power consumption of a design which would also protect the chips from permanent failure due to additional heat in the chips. Various power reduction methods including supply voltage scaling, dynamic voltage and frequency scaling, multi voltage design, clock gating for dynamic power reduction, and multi-Vth technique, power gating for leakage power reduction have been proposed. The main aim of our research was to reduce the supply voltage which has a quadruple e ffect on reducing the power consumption, and hence operate the designs in or as close to the subthreshold region of operation as possible. This kind of ultra low power designs are especially useful in biomedical applications. Carry skip adder and magnitude comparator designs are considered for our research due to the extensive use of such designs in almost all arithmetic applications. Simulations are performed at 45nm CMOS technology and at very low voltages, (e.g., 0.4V) to check the functionality first, followed by the application of some of the most widely used power reduction techniques in the industry, including clock gating and power gating, to test their eff ectiveness at such low voltages. Error detection sequential circuits were also employed to check if they can further reduce the power consumption and improve the performance of the designs with ultra low supply voltages. The results obtained give interesting insights into the e ffectiveness of various power reduction techniques at ultra low voltages.
Wen-Ben Jone, Ph.D. (Committee Chair)
Ranganadha Vemuri, Ph.D. (Committee Member)
Philip Wilsey, Ph.D. (Committee Member)
77 p.
Computer Engineering

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Citations

  • Varanasi, P. K. A. (2015). Study of Ultra Low Power Design and Power Reduction Techniques for VLSI Circuits at Ultra Low Voltages [Master's thesis, University of Cincinnati]. OhioLINK Electronic Theses and Dissertations Center. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1439307481

    APA Style (7th edition)

  • Varanasi, Phani Kameswara Abhishikth. Study of Ultra Low Power Design and Power Reduction Techniques for VLSI Circuits at Ultra Low Voltages. 2015. University of Cincinnati, Master's thesis. OhioLINK Electronic Theses and Dissertations Center, http://rave.ohiolink.edu/etdc/view?acc_num=ucin1439307481.

    MLA Style (8th edition)

  • Varanasi, Phani Kameswara Abhishikth. "Study of Ultra Low Power Design and Power Reduction Techniques for VLSI Circuits at Ultra Low Voltages." Master's thesis, University of Cincinnati, 2015. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1439307481

    Chicago Manual of Style (17th edition)

ucin1439307481
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© 2015, some rights reserved.Creative Commons License Study of Ultra Low Power Design and Power Reduction Techniques for VLSI Circuits at Ultra Low Voltages by Phani Kameswara Abhishikth Varanasi is licensed under a Creative Commons Attribution-NonCommercial-NoDerivs 3.0 Unported License. Based on a work at etd.ohiolink.edu.
This open access ETD is published by University of Cincinnati and OhioLINK.
Release 3.2.12