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Analysis of Booth’s Multiplier Algorithm vs Array Multiplier Algorithm and their FPGA Implementation

Gunturu, Anantha Sri Purnima

Abstract Details

2019, Master of Science in Engineering, Youngstown State University, Rayen School of Engineering.
The purpose of this study is to understand the Booth’s Multiplier algorithm for a 32-bit input and compare its performance with an Array Multiplier algorithm for a 32-bit input. The analysis involves implementing the developed VHDL design on an FPGA to understand and compare the performance of these multiplier algorithms. Efficient algorithms for signal processing are critical to very large-scale future applications such as video processing and four-dimensional medical imaging. Similarly, efficient algorithms are important for embedded and power-limited applications since, by reducing the number of computations, power consumption can be reduced considerably. A brief review of the multiplication process, implementation, and various multiplier algorithms have been included in this document to discuss and ease the understanding and objective of this study. Altera Prime Lite Quartus II version 18.1 was used for simulation of the models. DE10 Standard FPGA development board by Terasic Technologies was used for the hardware implementation of these VHDL models. After comparing the implementations of both 32-bit Array and Booth multiplier on a Cyclone V FPGA, a conclusion was made that the Booth multiplier has 56 Logic Elements versus 1,719 Logic Elements. Both the multipliers have shown comparable calculation performances.
Frank Li, PhD (Advisor)
Edward Burden, PhD (Committee Member)
Eric MacDonald, PhD (Committee Member)
41 p.

Recommended Citations

Citations

  • Gunturu, A. S. P. (2019). Analysis of Booth’s Multiplier Algorithm vs Array Multiplier Algorithm and their FPGA Implementation [Master's thesis, Youngstown State University]. OhioLINK Electronic Theses and Dissertations Center. http://rave.ohiolink.edu/etdc/view?acc_num=ysu1578311566143241

    APA Style (7th edition)

  • Gunturu, Anantha Sri Purnima. Analysis of Booth’s Multiplier Algorithm vs Array Multiplier Algorithm and their FPGA Implementation. 2019. Youngstown State University, Master's thesis. OhioLINK Electronic Theses and Dissertations Center, http://rave.ohiolink.edu/etdc/view?acc_num=ysu1578311566143241.

    MLA Style (8th edition)

  • Gunturu, Anantha Sri Purnima. "Analysis of Booth’s Multiplier Algorithm vs Array Multiplier Algorithm and their FPGA Implementation." Master's thesis, Youngstown State University, 2019. http://rave.ohiolink.edu/etdc/view?acc_num=ysu1578311566143241

    Chicago Manual of Style (17th edition)