A comparator with rail-to-rail input voltage range is presented. The rail-to-rail operation is achieved using two folded-cascode differential amplifiers operating in parallel as an input stage. The output of the appropriate amplifier is connected to the comparator output through a transmission-gate logic stage. Temperature-insensitivity is achieved by designing the input-stage amplifiers for zero-temperature-coefficient (ZTC) operation. The proposed comparator was simulated using 0.5µm silicon-on-insulator CMOS (SOI-CMOS) models. The circuit provides propagation delay less than 146.9ns. Over the 0V to 3.3V rail-to-rail common-mode input voltage range, the maximum input-offset voltage is less than 300µV at 27°C and less than 1.91mV over the temperature range of 27°C to 125°C.
The comparator is shown to be suitable for a successive-approximation-register analog-to-digital converter (SAR-ADC) application by a series of validation simulations. An 8-bit SAR-ADC incorporating the comparator was tested to determine its integral non-linearity (INL) and differential non-linearity (DNL). The SAR-ADC exhibited a worst-case INL of 0.6LSB and a worst-case DNL of 0.2LSB over the temperature range 27°C to 125°C. The SAR ADC is capable of completing one conversion every 15µs, which is adequate for sampling at a rate of 65 Kilo-samples per second (KSPS).