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VLSI testing for high reliability: Mixing IDDQ and logic testing

Hwang, Suntae
http://rave.ohiolink.edu/etdc/view?acc_num=case1056994488

Abstract Details

1993, Doctor of Philosophy, Case Western Reserve University, Computer Engineering.
Recently, it has been recognized that logic testing does not detect many physical defects such as bridging and open faults. In this study, we examine the effectiveness of combined logic and Iddq testing to detect stuck-at and bridging faults. The stuck-at faults are detected by logic testing by voltage measurement and Iddq testing detects bridging faults. Near-minimal stuck-at test sets are used for this combined logic and Iddq test environment. These near-minimal stuck-at test sets are generated using standard test programs, while using collapsed fault lists. We examined ISCAS '85 and ISCAS '89 benchmark circuits. A comparison is given for the fault coverage obtained under this combined test environment with other studies based on pure logic test and Iddq test. Also, the results of Iddq-based test sets (vectors generated specifically for Iddq testing) are compared with those of stuck-at test sets. To save the test effort, we also examine the bridging fault coverage in Iddq testing when partial stuck-at test sets are used. We present a case study on a microprogrammed processor using a functional test set in the combined test environment to detect logic and bridging faults. Based upon results obtained during this study, we established a relationship between stuck-at test sets and bridging fault coverage in Iddq testing, and finally, we suggest a guideline on the use of stuck-at test sets in Iddq environment.
Rochit Rajsuman (Advisor)
107 p.
VLSI testing; reliability; IDDQ; logic testing

Recommended Citations

Citations

  • Hwang, S. (1993). VLSI testing for high reliability: Mixing IDDQ and logic testing [Doctoral dissertation, Case Western Reserve University]. OhioLINK Electronic Theses and Dissertations Center. http://rave.ohiolink.edu/etdc/view?acc_num=case1056994488

    APA Style (7th edition)

  • Hwang, Suntae. VLSI testing for high reliability: Mixing IDDQ and logic testing. 1993. Case Western Reserve University, Doctoral dissertation. OhioLINK Electronic Theses and Dissertations Center, http://rave.ohiolink.edu/etdc/view?acc_num=case1056994488.

    MLA Style (8th edition)

  • Hwang, Suntae. "VLSI testing for high reliability: Mixing IDDQ and logic testing." Doctoral dissertation, Case Western Reserve University, 1993. http://rave.ohiolink.edu/etdc/view?acc_num=case1056994488

    Chicago Manual of Style (17th edition)

case1056994488
842
© 1993, all rights reserved.
This open access ETD is published by Case Western Reserve University School of Graduate Studies and OhioLINK.