Skip to Main Content
 

Global Search Box

 
 
 
 

Files

File List


case1057603424.pdf (7.01 MB)

ETD Abstract Container

Abstract Header

Area and delay estimation for constraint-driven high-level synthesis

Nourani-Dargiri, Mehrdad
http://rave.ohiolink.edu/etdc/view?acc_num=case1057603424

Abstract Details

1994, Doctor of Philosophy, Case Western Reserve University, Computer Engineering.
The flurry of activity in high level synthesis and its increasing popularity as a research topic, both in industry and academia, is a natural consequence of the progress in VLSI design technology and methodology. High level synthesis (HLS) fills the gap between behavioral level and layout level by automatically generating an RTL datapath realization from a behavioral description. The actual circuit layout can be generated later from the RTL datapath using a silicon compiler. A common characteristic of most HLS systems is the lack of consideration to the logic and layout synthesis aspects during the HLS process. The designs generated by these systems may or may not satisfy the initial design requirements and thus the design may need to be changed or modified. One method to address this deficiency is to use estimators, as a bridge between high and low levels, during HLS. The estimators can be iteratively invoked at high levels (e.g. scheduling and allocation) to provide a guiding mechanism to search the design space, which in turn leads to improved design quality and shorter design turnaround time. Motivated by the above observations, in this dissertation we present methods to cover the gap between high and low levels of design hierarchy, including: (1) Scheduling and mixed scheduling-allocation algorithms under time and resource constraints based on Liapunov stability theorem; (2) A neural network based scheduling as an alternative for implementing on parallel machines; (3) A layout estimation method which uses non-probabilistic analytical formulas in a constructive algorithm to estimate the overall area of a datapath; (4) A delay estimation algorithm which identifies false paths at the RTL and computes the static and dynamic critical delay in a datapath. Incorporation of these tools into an experimental HLS system, SYNTEST, has been completed with the overall objective of generating a structural VHDL description of a self-testable RTL datapath from a given behavioral VHDL specification.
Christos Papachristou (Advisor)
208 p.
constraint driven synthesis

Recommended Citations

Citations

  • Nourani-Dargiri, M. (1994). Area and delay estimation for constraint-driven high-level synthesis [Doctoral dissertation, Case Western Reserve University]. OhioLINK Electronic Theses and Dissertations Center. http://rave.ohiolink.edu/etdc/view?acc_num=case1057603424

    APA Style (7th edition)

  • Nourani-Dargiri, Mehrdad. Area and delay estimation for constraint-driven high-level synthesis. 1994. Case Western Reserve University, Doctoral dissertation. OhioLINK Electronic Theses and Dissertations Center, http://rave.ohiolink.edu/etdc/view?acc_num=case1057603424.

    MLA Style (8th edition)

  • Nourani-Dargiri, Mehrdad. "Area and delay estimation for constraint-driven high-level synthesis." Doctoral dissertation, Case Western Reserve University, 1994. http://rave.ohiolink.edu/etdc/view?acc_num=case1057603424

    Chicago Manual of Style (17th edition)

case1057603424
437
© 1994, all rights reserved.
This open access ETD is published by Case Western Reserve University School of Graduate Studies and OhioLINK.
Release 3.2.12