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Design and Analysis Methodologies to Reduce Soft Errors in nanometer VLSI Circuits

Gill, Balkaran S
http://rave.ohiolink.edu/etdc/view?acc_num=case1126207930

Abstract Details

2006, Doctor of Philosophy, Case Western Reserve University, Computer Engineering.
As process technology advances into Very Deep Sub-Micron (VDSM) level, CMOS VLSI system reliability is becoming a major concern. One of the main causes of reliability reduction is caused by charge particle strikes due to cosmic radiation which create soft errors, also referred to as Single Event Upsets (SEUs). In past technologies, this problem was limited to radiation hostile environments such as space. With VDSM designs, however, low energy particles at the ground level can cause soft errors, making CMOS circuits sensitive to atmospheric neutrons, as well as to alpha particles created by the unstable isotopes that can be found in materials of a chip. Soft errors are a major problem in mission critical applications where reliability is the main concern over performance and cost, such as heart defibrillators, avionics, etc. Our research focus is to provide design and analysis methodologies that reduce soft error in CMOS VLSI circuits implemented in nanometer process technologies. From the designer's point of view, a VLSI system consists of combinatorial logic, memory, and clock networks. We propose several design and analysis methodologies to reduce soft errors in logic, memories (SRAM), and clock networks. For logic, we pursue two different tracks: 1) Nodes sensitivity analysis and mitigation for soft errors in CMOS logic. 2) Soft Delay errors effects and analysis. For memories, we have developed an efficient Built-in Current Sensor (BICS) for the detection and localization of SEUs. We use a combination of BICS and ECC for single as well as multiple errors correction in SRAM. For the clock networks, we have analyzed the radiation-induced clock jitters and race. Our results for various test circuits show that the accuracy achieved by our analysis approaches is close to Spice and, at the same time, they are several orders of magnitude faster than Spice. We reduced the sensitivity of nodes by applying electrical hardening technique on highly sensitive nodes which were determined by our approaches. The reliability analysis of our new BICS shows that it can work under process, voltage, and temperature variations as well as in harsh noise environments.
Christos Papachristou (Advisor)
164 p.
nanometer; SEU; SMU; Soft errors; Soft Delay; BICS; Clock jitters; race; radiation; neutron; alpha-particles

Recommended Citations

Citations

  • Gill, B. S. (2006). Design and Analysis Methodologies to Reduce Soft Errors in nanometer VLSI Circuits [Doctoral dissertation, Case Western Reserve University]. OhioLINK Electronic Theses and Dissertations Center. http://rave.ohiolink.edu/etdc/view?acc_num=case1126207930

    APA Style (7th edition)

  • Gill, Balkaran. Design and Analysis Methodologies to Reduce Soft Errors in nanometer VLSI Circuits. 2006. Case Western Reserve University, Doctoral dissertation. OhioLINK Electronic Theses and Dissertations Center, http://rave.ohiolink.edu/etdc/view?acc_num=case1126207930.

    MLA Style (8th edition)

  • Gill, Balkaran. "Design and Analysis Methodologies to Reduce Soft Errors in nanometer VLSI Circuits." Doctoral dissertation, Case Western Reserve University, 2006. http://rave.ohiolink.edu/etdc/view?acc_num=case1126207930

    Chicago Manual of Style (17th edition)

case1126207930
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© 2005, all rights reserved.
This open access ETD is published by Case Western Reserve University School of Graduate Studies and OhioLINK.