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Data Transfer System for Host Computer and FPGA Communication

Barnard, Michael T.
http://rave.ohiolink.edu/etdc/view?acc_num=dayton1448287709

Abstract Details

2015, Master of Science (M.S.), University of Dayton, Electrical Engineering.
This Thesis describes a communication system to allow for the transmission of data between a host computer and a DE2-115 FPGA board over an Ethernet connection. This is achieved by using a socket between the host computer and a NIOS II embedded processor that accepts the data from the host computer and transfers it to the FPGA fabric. The host computer uses a C++ program to open a file and send the data over the socket to the NIOS II processor. The NIOS II acts as memory controller for the Synchronous Dynamic Random Access Memory (SDRAM) on the board with separate input and output data sections for the Hardware Description Language (HDL) processing module. A HDL module then processes the data and sends it back to the NIOS II to be returned to the host computer over the socket. The data transfer system is tested with three basic image processing functions performed on three sample images to verify its functionality. This data transfer system allows for easier testing of digital designs on the DE2-115 board by providing test data to the digital design in an efficient manner.
Eric Balster, Ph.D. (Committee Chair)
John Weber, Ph.D. (Committee Member)
Tarek Taha, Ph.D. (Committee Member)
47 p.
Electrical Engineering
Data Transfer; FPGA Board; NIOS II Processor; Sockets; Ethernet; TCP IP

Recommended Citations

Citations

  • Barnard, M. T. (2015). Data Transfer System for Host Computer and FPGA Communication [Master's thesis, University of Dayton]. OhioLINK Electronic Theses and Dissertations Center. http://rave.ohiolink.edu/etdc/view?acc_num=dayton1448287709

    APA Style (7th edition)

  • Barnard, Michael. Data Transfer System for Host Computer and FPGA Communication. 2015. University of Dayton, Master's thesis. OhioLINK Electronic Theses and Dissertations Center, http://rave.ohiolink.edu/etdc/view?acc_num=dayton1448287709.

    MLA Style (8th edition)

  • Barnard, Michael. "Data Transfer System for Host Computer and FPGA Communication." Master's thesis, University of Dayton, 2015. http://rave.ohiolink.edu/etdc/view?acc_num=dayton1448287709

    Chicago Manual of Style (17th edition)

dayton1448287709
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This open access ETD is published by University of Dayton and OhioLINK.