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Design and Implementation of an FPGA-Based Scalable Pipelined Associative SIMD Processor Array with Specialized Variations for Sequence Comparison and MSIMD Operation

Wang, Hong
http://rave.ohiolink.edu/etdc/view?acc_num=kent1164126183

Abstract Details

2006, PHD, Kent State University, College of Arts and Sciences / Department of Computer Science.
Over the years a number of variations on associative computing have been explored. At Kent State University (KSU), associative SIMD computing has its roots at Goodyear Aerospace Corporation, but most recently has focused on exploring the power of the associative computing paradigm as compared to traditional SIMD, and even MIMD, computing. In contrast, Prof. Robert Walker’s research group at KSU has focused on implementing those associative concepts on a single chip by developing a new associative SIMD RISC processor, called the ASC (ASsociative Computing) Processor, using modern FPGA implementation techniques. This dissertation describes the development of a working, scalable, ASC Processor that is pipelined to improve performance, supports a reconfigurable network, can be specialized further for dedicated applications (e.g., genome processing), and that can realize the multiple SIMD (MSIMD) paradigm by supporting multiple control units. As a first step in this processor development, a Control Unit and a 4-PE Array developed previously by Master’s students were integrated into the first working ASC Processor. This processor was then modified to develop the first scalable PE ASC Processor, and demonstrated on database processing and image processing. However, the core of this dissertation research was the design and implementation of a pipelined scalable ASC Processor, which as far as we are aware is the first working single-chip pipelined SIMD associative processor and perhaps the first single-chip pipelined SIMD processor in general. Compared to the first scalable ASC Processor, this pipelined processor not only gains the advantage of pipelining, but has a faster clock frequency due to a more efficient implementation. With that pipelined scalable ASC Processor as a base, two major architectural variations were explored. To support an innovative LCS algorithm for genome sequence comparison, the reconfigurable PE interconnection was modified with some features inspired by the coterie network, plus row and column broadcast buses. To better support control parallelism and increase PE utilization, a multiple-instruction-stream MASC Processor was developed, which dynamically assigns tasks to Processing Elements as the program executes.
Robert Walker (Advisor)
81 p.
Computer Science
Parallel Computing; Parallel Processing; FPGA; ASC; MASC; Associative Computing; Associative Processing; Parallel Processor Design.

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Citations

  • Wang, H. (2006). Design and Implementation of an FPGA-Based Scalable Pipelined Associative SIMD Processor Array with Specialized Variations for Sequence Comparison and MSIMD Operation [Doctoral dissertation, Kent State University]. OhioLINK Electronic Theses and Dissertations Center. http://rave.ohiolink.edu/etdc/view?acc_num=kent1164126183

    APA Style (7th edition)

  • Wang, Hong. Design and Implementation of an FPGA-Based Scalable Pipelined Associative SIMD Processor Array with Specialized Variations for Sequence Comparison and MSIMD Operation. 2006. Kent State University, Doctoral dissertation. OhioLINK Electronic Theses and Dissertations Center, http://rave.ohiolink.edu/etdc/view?acc_num=kent1164126183.

    MLA Style (8th edition)

  • Wang, Hong. "Design and Implementation of an FPGA-Based Scalable Pipelined Associative SIMD Processor Array with Specialized Variations for Sequence Comparison and MSIMD Operation." Doctoral dissertation, Kent State University, 2006. http://rave.ohiolink.edu/etdc/view?acc_num=kent1164126183

    Chicago Manual of Style (17th edition)

kent1164126183
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© 2006, all rights reserved.
This open access ETD is published by Kent State University and OhioLINK.