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Fault simulation for stuck-open faults in CMOS combinational circuits

Su, Lang
http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1176236480

Abstract Details

1993, Master of Science (MS), Ohio University, Electrical Engineering & Computer Science (Engineering and Technology).

Fault simulation for stuck-open faults in CMOS combinational circuits

M. Mokari (Advisor)
90 p.
Fault Simulation; Stuck-Open Faults; CMOS; Combinational Circuits

Recommended Citations

Citations

  • Su, L. (1993). Fault simulation for stuck-open faults in CMOS combinational circuits [Master's thesis, Ohio University]. OhioLINK Electronic Theses and Dissertations Center. http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1176236480

    APA Style (7th edition)

  • Su, Lang. Fault simulation for stuck-open faults in CMOS combinational circuits. 1993. Ohio University, Master's thesis. OhioLINK Electronic Theses and Dissertations Center, http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1176236480.

    MLA Style (8th edition)

  • Su, Lang. "Fault simulation for stuck-open faults in CMOS combinational circuits." Master's thesis, Ohio University, 1993. http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1176236480

    Chicago Manual of Style (17th edition)

ohiou1176236480
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© 1993, all rights reserved.
This open access ETD is published by Ohio University and OhioLINK.