A third generation mobile system is scheduled for launch in 2002. The system provides a high data rate that can be used for multimedia and internet services. As the diversity of required services and performance of the mobile units increases, the traditional hardware implementation of the mobile terminal will fall short of providing the required flexibility and performance. This justifies the use of reconfigurable hardware.
The typical implementations of the current mobile systems are a mixture of ASICs and DSPs. ASICs are used for their high performance and low power. DSPs are used for their flexibility. The two implementation paradigms are combined in this research to reach a compromise between low cost, low power consumption (long battery life), flexibility, and performance.
A dynamically reconfigurable computing architecture is an ideal implementation solution for the third and future generations of mobile systems. This dissertation delineates the design and simulation of a new dynamically reconfigurable architecture called DRAW. DRAW is a hardware fabric specially designed for the third generation wireless mobile systems.
Reconfigurable computing lowers the cost of the final product by shortening the time to market period through the reduction of the design flow steps. Additionally, it reduces the power consumption through the dynamic switching on the required hardware logic, while avoiding the excessive area requirements of dedicated ASICs.
A Matlab simulation test bed was written and used to extract the main characteristics of the target application. Once a broad guidelines of the design process were available, a synthesizeable VHDL description of the architecture was written. The design of the architecture was further optimized through iterative post-synthesize simulations and redesign.
A further work is needed in three main points, firstly, optimize the architecture for power, secondly, develop an automated mapping tools for mapping dif-ferent baseband algorithms onto the architecture, thirdly, construct a set of intellectual property blocks for wireless communication to be mapped into the designed hardware fabric.