Skip to Main Content
Frequently Asked Questions
Submit an ETD
Global Search Box
Need Help?
Keyword Search
Participating Institutions
Advanced Search
School Logo
Files
File List
ohiou1204910134.pdf (2.65 MB)
ETD Abstract Container
Abstract Header
Implementation of Hopfield Neural Network Using Double Gate MOSFET
Author Info
Borundiya, Amit Parasmal
Permalink:
http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1204910134
Abstract Details
Year and Degree
2008, Master of Science (MS), Ohio University, Electrical Engineering & Computer Science (Engineering and Technology).
Abstract
Hopfield Neural Network has been used to solve the constraints satisfaction problems. To make these networks solve problem in real time, independent of the size, would require building a massively parallel structure. A CMOS circuit can be used to construct such network to find the solution. Current CMOS technology is reaching its physical limitation in deep submicron regime and new devices are explored which can provide scalability in accordance to Moore's; Law. To further increase the network capacity double gate transistors can be used. Double gate MOSFET model of the hysteresis neuron proposed in this thesis utilizes 8 transistors as compared to 60 transistors needed with an operational amplifier's; model. This structure not only reduces the count of transistors by 86% but also demonstrates that larger circuits of double gate MOSFETs can be built, bolstering the faith in double gate MOSFET devices as a possible substitute of CMOS devices in a near future.
Committee
Janusz A. Starzyk, PhD (Committee Chair)
Savas Kaya, PhD (Committee Member)
Jeffery Dill, PhD (Committee Member)
Xiaoping Shen, PhD (Committee Member)
Pages
95 p.
Subject Headings
Electrical Engineering
Keywords
Hysteresis Hopfield Neural Network using double gate MOSFET
;
double gate mosfet neural network
;
N-Queen with double gate MOSFET
Recommended Citations
Refworks
EndNote
RIS
Mendeley
Citations
Borundiya, A. P. (2008).
Implementation of Hopfield Neural Network Using Double Gate MOSFET
[Master's thesis, Ohio University]. OhioLINK Electronic Theses and Dissertations Center. http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1204910134
APA Style (7th edition)
Borundiya, Amit.
Implementation of Hopfield Neural Network Using Double Gate MOSFET.
2008. Ohio University, Master's thesis.
OhioLINK Electronic Theses and Dissertations Center
, http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1204910134.
MLA Style (8th edition)
Borundiya, Amit. "Implementation of Hopfield Neural Network Using Double Gate MOSFET." Master's thesis, Ohio University, 2008. http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1204910134
Chicago Manual of Style (17th edition)
Abstract Footer
Document number:
ohiou1204910134
Download Count:
2,788
Copyright Info
© 2008, all rights reserved.
This open access ETD is published by Ohio University and OhioLINK.
Release 3.2.12