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High-Frequency Oscillator Design with Independent Gate FinFET

Kelestemur, Yunus

Abstract Details

2019, Master of Science (MS), Ohio University, Electrical Engineering & Computer Science (Engineering and Technology).
There is an increasing demand for wireless communication because of its convenience for the system-on-chip (SoC) paradigm that integrates the whole system on a single chip. Most of SoC applications such as 5G mobile network, car radar, network-onchip (NoC) communication require high-frequency oscillators. In particular, the wireless links that can be adapted for on-chip communication can greatly expand the power and latency concerns in future many-core (64 and above) computers. The transmitters in the NoC routers would need very high-frequency wireless channels that must be driven by extremely compact and efficient oscillators that can operate as high as 500 GHz. In this thesis, two high-frequency voltage-controlled oscillators are presented without using any varactors to control the frequency of oscillation. The independent gate (IG) FinFETs are used to tune the oscillation frequency of the oscillators and simulations are carried out using Cadence Virtuoso design tools and BSIM-IMG transistor models inserted into a 65 nm RF-CMOS design kit. The first oscillator design is based on Colpitts architecture using 65 nm IG-FinFETs. The oscillator has 165 GHz oscillation frequency with 3% tunability. The power consumption of the oscillator is 50mW and the area is less than 0.001mm2. The phase noise of the oscillator at 1 MHz is -70 dBc/Hz. The second oscillator design is based on the cross-coupled push-push oscillator architecture using 45 nm IG-FinFETs. The oscillator has 250 GHz oscillation frequency with 2% tunability. The power consumption of the oscillator is 12 mW and the area is less than 0.01mm2. The phase noise of the oscillator at 1 MHz is -82 dBc/Hz. Besides the novel oscillator topologies and their encouraging performance figures, this work also incorporates several other unique aspects, including the use of BSIM-IMG based models in connection with an RF-CMOS design kit, utilization of tunable transistor parasitics for VCO design and incorporation of accurate modeling of 3D inductors obtained via 3D electro-magnetic solvers into the circuit analysis. Although the performance predictions are limited by the finite accuracy of the BSIM model at such elevated frequencies and by the lack of detailed layout rules for the IG-FinFETs, the work performed in this thesis lends strong credence to this transistor architecture for compact circuit development in analog mm-wave circuits in general and SoC wireless applications in particular.
savas kaya, Dr. (Advisor)
avinash karanth, Dr. (Committee Member)
wojciech jadwisienczak, Dr. (Committee Member)
eric stinaff, Dr. (Committee Member)
68 p.

Recommended Citations

Citations

  • Kelestemur, Y. (2019). High-Frequency Oscillator Design with Independent Gate FinFET [Master's thesis, Ohio University]. OhioLINK Electronic Theses and Dissertations Center. http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1574781254788344

    APA Style (7th edition)

  • Kelestemur, Yunus. High-Frequency Oscillator Design with Independent Gate FinFET. 2019. Ohio University, Master's thesis. OhioLINK Electronic Theses and Dissertations Center, http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1574781254788344.

    MLA Style (8th edition)

  • Kelestemur, Yunus. "High-Frequency Oscillator Design with Independent Gate FinFET." Master's thesis, Ohio University, 2019. http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1574781254788344

    Chicago Manual of Style (17th edition)