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Designing Low Power and High Performance Network-on-Chip Communication Architectures for Nanometer SoCs

Reehal, Gursharan Kaur
http://rave.ohiolink.edu/etdc/view?acc_num=osu1340022240

Abstract Details

2012, Doctor of Philosophy, Ohio State University, Electrical and Computer Engineering.
Network-on-Chip (NoC) communication architectures have been recognized as the most scalable and efficient solution for on chip communication challenges in the multi-core era. Diverse demanding applications coupled with the ability to integrate billions of transistors on a single chip are some of the main driving forces behind ever increasing performance requirements towards the level that requires several tens to over a hundred of cores per chip. Small scale multicore processors so far have been a great commercial success and found applicability in many applications. Systems using multi-core processors are now the norm rather than the exception. As the number of cores or components integrated into a single system is keep increasing, the design of on-chip communication architecture is becoming more challenging. The increasing number of components in a system translates into more inter-component communication that must be handled by the on-chip communication infrastructure. Future system-on-chip (SoC) designs require predictable, scalable and reusable on-chip communication architectures to increase reliability and productivity. Current bus-based interconnect architectures are inherently non-scalable, less adaptable for reuse and their reliability decreases with system size. NoC communication guarantees scalability, high-speed, high-bandwidth communication with minimal wiring overhead and routing issues. NoCs are layered, packet-based on-chip communication networks integrated onto a single chip. NoC consists of resources and switches that are directly connected in a way that resources are able to communicate with each other by sending messages. The proficiency of a NoC to meet its design goals and budget requirements for the target application depends on its design. Often, these design goals conflict and trade-off with each other. The multi-dimensional pull of design constraints in addition to technology scaling complicates the process of NoC design in many aspects, as they are expected to support high performance and reliability along with low cost, smaller area, less time-to-market and lower power consumption. To aid in the process, this research presents design methodologies to achieve low power and high performance NoC communication architectures for nanometer SoCs.
Mohammed Ismail El-Naggar, Dr. (Advisor)
Steve Bibyk, Dr. (Committee Member)
Joanne DeGroat, Dr. (Committee Member)
189 p.
Electrical Engineering
Network-on-Chip (NoC); System-on-Chip (SoC); NoC Interconnects; NoC Power Modeling; Low Power NoC design; Cliche Network; BFT Network; SPIN Network; Octagon Network; Asynchronous NoC design; Power Models

Recommended Citations

Citations

  • Reehal, G. K. (2012). Designing Low Power and High Performance Network-on-Chip Communication Architectures for Nanometer SoCs [Doctoral dissertation, Ohio State University]. OhioLINK Electronic Theses and Dissertations Center. http://rave.ohiolink.edu/etdc/view?acc_num=osu1340022240

    APA Style (7th edition)

  • Reehal, Gursharan. Designing Low Power and High Performance Network-on-Chip Communication Architectures for Nanometer SoCs. 2012. Ohio State University, Doctoral dissertation. OhioLINK Electronic Theses and Dissertations Center, http://rave.ohiolink.edu/etdc/view?acc_num=osu1340022240.

    MLA Style (8th edition)

  • Reehal, Gursharan. "Designing Low Power and High Performance Network-on-Chip Communication Architectures for Nanometer SoCs." Doctoral dissertation, Ohio State University, 2012. http://rave.ohiolink.edu/etdc/view?acc_num=osu1340022240

    Chicago Manual of Style (17th edition)

osu1340022240
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© 2012, all rights reserved.
This open access ETD is published by The Ohio State University and OhioLINK.