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Duncan_Dissertation_20170421.pdf (6.65 MB)

ETD Abstract Container

Abstract Header

A 10-bit DC-20 GHz Multiple-Return-to-Zero DAC with >48 dB SFDR

Duncan, Lucas
http://rave.ohiolink.edu/etdc/view?acc_num=osu1492740839889776

Abstract Details

2017, Doctor of Philosophy, Ohio State University, Electrical and Computer Engineering.
Recent trends in 5G and radar systems have revealed the need for high-frequency DACs with minimal spurious emissions. Amplitude and timing errors in the DAC have proven to be a significant hindrance to linearity performance and have an increasing impact with frequency. Primary contributors to these errors are impedance mismatches in the current combining network as well as device mismatches. This work presents a frequency-domain approach to SFDR analysis in which the contribution of each individual cell on the output spectrum is analyzed and errors are applied as transfer functions in the frequency domain. Using this method, static amplitude and timing errors can be examined through a Monte Carlo (MC) analysis using only numerical computation, thus eliminating the need to run a transient simulation for each MC sample. Moreover, unlike the conventional analysis, the frequency-domain approach is amenable to the small-signal models produced by EM simulations, enabling the incorporation of complex output summing node structures with little impact to simulation time and convergence. The frequency-domain analysis is used to produce a 10-bit 3.35 Gsps MRZ DAC capable of synthesizing frequencies from DC to 20 GHz with greater than 48 dB} SFDR. The design includes a vertically-stacked tree (VST) interconnect structure that minimizes attenuation and phase mismatches in the output summing node. Additionally, a per-cell timing adjustment circuit is proposed, which, along with static current calibration, is used to minimize the remaining errors. Measurement results show that the calibration provides up to 7 dB improvement in SFDR at 20 GHz. The combination of the VST and calibration techniques yield the highest reported SFDR at 20 GHz, while synthesizing the highest instantaneous bandwidth among RF DACs.
Waleed Khalil (Advisor)
Steven Bibyk (Advisor)
Ayman Fayed (Committee Member)
Electrical Engineering

Recommended Citations

Citations

  • Duncan, L. (2017). A 10-bit DC-20 GHz Multiple-Return-to-Zero DAC with >48 dB SFDR [Doctoral dissertation, Ohio State University]. OhioLINK Electronic Theses and Dissertations Center. http://rave.ohiolink.edu/etdc/view?acc_num=osu1492740839889776

    APA Style (7th edition)

  • Duncan, Lucas. A 10-bit DC-20 GHz Multiple-Return-to-Zero DAC with >48 dB SFDR. 2017. Ohio State University, Doctoral dissertation. OhioLINK Electronic Theses and Dissertations Center, http://rave.ohiolink.edu/etdc/view?acc_num=osu1492740839889776.

    MLA Style (8th edition)

  • Duncan, Lucas. "A 10-bit DC-20 GHz Multiple-Return-to-Zero DAC with >48 dB SFDR." Doctoral dissertation, Ohio State University, 2017. http://rave.ohiolink.edu/etdc/view?acc_num=osu1492740839889776

    Chicago Manual of Style (17th edition)

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© 2017, all rights reserved.
This open access ETD is published by The Ohio State University and OhioLINK.