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Capacitively-Coupled, Pseudo Return-to-Zero Input, Latched-Bias Data Receiver

Mathieu, Brandon Lee
http://orcid.org/0000-0002-4830-2150
http://rave.ohiolink.edu/etdc/view?acc_num=osu1543502773721236

Abstract Details

2018, Doctor of Philosophy, Ohio State University, Electrical and Computer Engineering.
The ever-increasing demand for data throughput from both wired and wireless networks is continuously burdening high-speed chip-to-chip links. With proposed processor-memory interface standards exceeding multiple Tb/s of data and leading-edge data converters requiring tens of Gb/s of data, power and area efficient data transfer is of utmost importance. This work focuses on the development of a small, low-power, fully-integrated, clock-less capacitively-coupled data receiver. The architecture utilizes small on-chip termination and coupling capacitors in order to avoid parasitics, impedance discontinuities and density limitations associated with their board-mounted counterparts. The small coupling capacitors transforms non-return to zero data streams into bi-polar return-to-zero pulse trains. The pulses’ polarities are digitally latched into the receiver via input bias switches, generating pseudo return-to-zero (PRZ) waveforms that reduces baseline wander and eliminates the need for data encoding or scrambling. A model of the PRZ signal is presented and compared to traditional AC coupled pulse receivers. Common mode feedback is included in the core of the receiver to account for process, voltage and temperature variation and mitigate duty-cycle distortion. Enhanced bandwidth digital inverters amplify the signal into a low-jitter full-scale digital signal that can directly interface with standard digital cell libraries, while rail-to-rail digital feedback serves as the digital control signals for the bias switches. The coupling scheme enables a wide acceptable input common-mode range and compatibility with legacy applications targeted for short chip-to-chip links in die stacking and heterogeneous integrated packing solutions. A 130 nm SiGe BiCMOS implementation of the receiver was analyzed, re-packaged and re-tested. Wire-bond inductance is eliminated via stud bumping and flip-chip die-on-board attachment. Calibrated testing resulted in a peak data rate of 10 Gb/s while consuming 5.1 mW and generating 23.2 ps p-p jitter. A peak power efficiency of 0.46 mW/Gb/s with 29.4 ps p-p jitter was realized at 8 Gb/s. An optimized implementation of the PRZ receiver was fabricated in a 45nm CMOS silicon-on-insulator (SOI) process. This design includes broadband termination, reduced coupling capacitance, eliminated level-shifting, and minimized feedback delay. Testing revealed a peak data rate of 30 Gb/s with 7.8 p-p jitter and consuming 12.02 mW. A peak efficiency of 0.24 mW/Gb/s was recorded at 24 Gb/s with 15.0 ps p-p jitter. Both the SiGe BiCMOS and CMOS SOI designs exhibit BERs less than 10-12 with PRBS15 data as small as 100 mV peak-to-peak amplitude and occupy 0.012 mm2 and 0.007 mm2, respectively, including the on-chip coupling capacitance.
Waleed Khalil (Advisor)
Bibyk Steven (Committee Member)
Dupaix Brian (Committee Member)
Miri Lavasani Hossein (Committee Member)
Musah Tawfiq (Committee Member)
97 p.
Electrical Engineering; Engineering
Baseline Wander; BiCMOS Integrated Circuits; CMOS SOI; Capacitive Coupling; Digital Feedback; Latch; Pulse Reciever;

Recommended Citations

Citations

  • Mathieu, B. L. (2018). Capacitively-Coupled, Pseudo Return-to-Zero Input, Latched-Bias Data Receiver [Doctoral dissertation, Ohio State University]. OhioLINK Electronic Theses and Dissertations Center. http://rave.ohiolink.edu/etdc/view?acc_num=osu1543502773721236

    APA Style (7th edition)

  • Mathieu, Brandon. Capacitively-Coupled, Pseudo Return-to-Zero Input, Latched-Bias Data Receiver. 2018. Ohio State University, Doctoral dissertation. OhioLINK Electronic Theses and Dissertations Center, http://rave.ohiolink.edu/etdc/view?acc_num=osu1543502773721236.

    MLA Style (8th edition)

  • Mathieu, Brandon. "Capacitively-Coupled, Pseudo Return-to-Zero Input, Latched-Bias Data Receiver." Doctoral dissertation, Ohio State University, 2018. http://rave.ohiolink.edu/etdc/view?acc_num=osu1543502773721236

    Chicago Manual of Style (17th edition)

osu1543502773721236
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© 2018, all rights reserved.
This open access ETD is published by The Ohio State University and OhioLINK.