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RomanFragasseMSThesisFinal.pdf (2.1 MB)

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A High-Speed Self-Timed SRAM with Offset Cancellation inthe IBM .13µm BiCMOS (8HP) Process

Fragasse, Roman Augustus
http://rave.ohiolink.edu/etdc/view?acc_num=osu1543570399314152

Abstract Details

2018, Master of Science, Ohio State University, Electrical and Computer Engineering.
This thesis presents work on the design of a 10 Kb, 500 MHz, self-timed, static random-access memory (SRAM) in the IBM8HP 0.13µm BiCMOS process. A high-speed SRAM architecture intended for fast caches, serial code accelerators, and high-speed processors was implemented and fabricated in the IBM8HP process. Simulation results show operation at above the targeted 500 MHz operating speed free of read-failure. A preliminary test plan has been developed, and measured results will be obtained for the memory from a printed circuit board (PCB) capable of measuring all of the pertinent characteristics. In addition to the fabricated SRAM design, a novel current-mode sense amplifier (CSA) topology has been proposed to work within the current architecture. Simulation results show up to a 30% reduction in the total read-access time (RDt) and thus a proportional improvement in the speed of the memory.
Waleed Khalil, Dr. (Advisor)
Steven Bibyk, Dr. (Advisor)
93 p.
Electrical Engineering
SRAM, High-Speed, IBM8HP, Input-Referred, Offset, Cancellation

Recommended Citations

Citations

  • Fragasse, R. A. (2018). A High-Speed Self-Timed SRAM with Offset Cancellation inthe IBM .13µm BiCMOS (8HP) Process [Master's thesis, Ohio State University]. OhioLINK Electronic Theses and Dissertations Center. http://rave.ohiolink.edu/etdc/view?acc_num=osu1543570399314152

    APA Style (7th edition)

  • Fragasse, Roman. A High-Speed Self-Timed SRAM with Offset Cancellation inthe IBM .13µm BiCMOS (8HP) Process. 2018. Ohio State University, Master's thesis. OhioLINK Electronic Theses and Dissertations Center, http://rave.ohiolink.edu/etdc/view?acc_num=osu1543570399314152.

    MLA Style (8th edition)

  • Fragasse, Roman. "A High-Speed Self-Timed SRAM with Offset Cancellation inthe IBM .13µm BiCMOS (8HP) Process." Master's thesis, Ohio State University, 2018. http://rave.ohiolink.edu/etdc/view?acc_num=osu1543570399314152

    Chicago Manual of Style (17th edition)

osu1543570399314152
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© 2018, all rights reserved.
This open access ETD is published by The Ohio State University and OhioLINK.