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Thesis - Priyanka Gadde.pdf (3.98 MB)

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Abstract Header

A BIST Architecture for Testing LUTs in a Virtex-4 FPGA

Gadde, Priyanka
http://rave.ohiolink.edu/etdc/view?acc_num=toledo1375316199

Abstract Details

2013, Master of Science in Electrical Engineering, University of Toledo, College of Engineering.
Field Programmable Gate Arrays (FPGAs) are programmable logic devices that can be used to implement a given digital design. Built-In Self-Test (BIST) is a testing technique that enables the device to test itself without the need for any external test equipment. The re-programmability feature of the FPGAs makes BIST a favorable approach for testing FPGAs because it eliminates any area or performance degradation associated with BIST. In order to ensure proper operation of Look up Tables in Xilinx Virtex-4 Field-Programmable Gate Arrays (FPGAs), a dependable and resource efficient test technique is needed so that the functional operation of the memory can be tested. Traditional BIST techniques for FPGAs suffer from a large number of logic resource requirements and long test times in the implementation and testing of the circuit. The work presented in this research simplifies the BIST architecture and reduces the test time required to test the Look up Tables in a Virtex-4 FPGA. The proposed technique is capable of testing the following types of memory faults: stuck-at fault, transition fault, address decoder fault, incorrect read fault, read destructive fault, deceptive read destructive fault, data retention fault, state coupling fault, transition coupling fault, incorrect read coupling fault, read destructive coupling fault, and deceptive read destructive coupling fault in a SRAM based FPGA.
Niamat Mohammed (Advisor)
Alam Mansoor (Committee Member)
Sun Weiqing (Committee Member)
134 p.
Electrical Engineering
BIST; SRAM; Faults; Memory; Virtex-4 FPGA; Read Faults; Write Faults; Built in Self-Test

Recommended Citations

Citations

  • Gadde, P. (2013). A BIST Architecture for Testing LUTs in a Virtex-4 FPGA [Master's thesis, University of Toledo]. OhioLINK Electronic Theses and Dissertations Center. http://rave.ohiolink.edu/etdc/view?acc_num=toledo1375316199

    APA Style (7th edition)

  • Gadde, Priyanka. A BIST Architecture for Testing LUTs in a Virtex-4 FPGA. 2013. University of Toledo, Master's thesis. OhioLINK Electronic Theses and Dissertations Center, http://rave.ohiolink.edu/etdc/view?acc_num=toledo1375316199.

    MLA Style (8th edition)

  • Gadde, Priyanka. "A BIST Architecture for Testing LUTs in a Virtex-4 FPGA." Master's thesis, University of Toledo, 2013. http://rave.ohiolink.edu/etdc/view?acc_num=toledo1375316199

    Chicago Manual of Style (17th edition)

toledo1375316199
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© 2013, all rights reserved.
This open access ETD is published by University of Toledo and OhioLINK.