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THE PERFORMANCE EVALUATION OF VHDL-AMS SIMULATORS BY CREATING LARGE, SCALABLE VHDL-AMS MODELS

BAPAT, SACHIN VASUDEO

Abstract Details

2002, MS, University of Cincinnati, Engineering : Computer Engineering.
A circuit simulator is an essential tool for every electronic design engineer. As many modern electronic systems contain a digital as well as an analog circuitry, a mixed-signal simulator is becoming an essential element for the modern design environment. A mixed-signal simulator typically consists of a digital kernel, an analog kernel and a method for synchronization. Analog kernels execute slowly compared to the digital kernels and thus are computationally expensive. Hence the developers of mixed-signal simulators should aim at reducing the simulation time by analyzing the simulator performance. This research is on the creation and an application of large, scalable models to evaluate the performance of VHDL-AMS simulators. We have created two VHDL-AMS models that scale and that possess a rich set of language features. One is termed as a RLC model and the other one as a SRAM model. The simulator performance was measured and analyzed by simulating the two models on a mixed-signal simulator. For this research, we have used a Sierra mixed-signal simulator developed at University of Cincinnati.
Dr. Harold Carter (Advisor)
95 p.

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Citations

  • BAPAT, S. V. (2002). THE PERFORMANCE EVALUATION OF VHDL-AMS SIMULATORS BY CREATING LARGE, SCALABLE VHDL-AMS MODELS [Master's thesis, University of Cincinnati]. OhioLINK Electronic Theses and Dissertations Center. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1032179532

    APA Style (7th edition)

  • BAPAT, SACHIN. THE PERFORMANCE EVALUATION OF VHDL-AMS SIMULATORS BY CREATING LARGE, SCALABLE VHDL-AMS MODELS. 2002. University of Cincinnati, Master's thesis. OhioLINK Electronic Theses and Dissertations Center, http://rave.ohiolink.edu/etdc/view?acc_num=ucin1032179532.

    MLA Style (8th edition)

  • BAPAT, SACHIN. "THE PERFORMANCE EVALUATION OF VHDL-AMS SIMULATORS BY CREATING LARGE, SCALABLE VHDL-AMS MODELS." Master's thesis, University of Cincinnati, 2002. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1032179532

    Chicago Manual of Style (17th edition)