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AN EFFICIENT BUILT-IN SELF-DIAGNOSTIC METHOD FOR NON-TRADITIONAL FAULTS OF EMBEDDED MEMORY ARRAYS

ARORA, VIKRAM
http://rave.ohiolink.edu/etdc/view?acc_num=ucin1037998809

Abstract Details

2002, MS, University of Cincinnati, Engineering : Computer Engineering.
With improvements in VLSI technology, more and more components are fabricated onto a single chip. The importance of system on chip (SoC) is growing rapidly in this era. It is estimated that the percentage of chip area occupied by embedded memory arrays on a SoC will rise to as high as 94% in the next decade. Even worse, memory arrays are more vulnerable to fabrication defects due to the higher packing density of transistors. If some cells of the embedded memory arrays on a SoC are defective, it is not economical to throw the chip away. The solution to this problem lies in designing an intelligent piece of built-in hardware which tests, diagnoses, and repairs the faulty cells of embedded memory arrays. In this thesis, we propose a built-in self-diagnostic march-based algorithm which identifies memory cells as faulty based on a recently introduced non-traditional fault model. This algorithm is developed based on the DiagRSMarch algorithm which is a diagnosis algorithm for embedded memory arrays for identifying traditional faults in memories. A minimal set of additional operations is added to DiagRSMarch for identifying the non-traditional faults without affecting the diagnostic coverage of the traditional faults. The embedded memory arrays are accessed using the bi-directional serial interfacing architecture which minimizes the routing overhead introduced by the diagnosis hardware. Using the concepts of serial interfacing technique, parallel testing and redundant-tolerant operations, the diagnosis process is accomplished efficiently at-speed with minimal hardware overhead. An implementation of the diagnosis algorithm is achieved in the form of a built-in self-diagnosis (BISD) controller with the memory arrays and their associated interfaces. The BISD Controller interacts closely with the built-in self-repair logic via suitable control signals. Ideally, we expect to have a single controller performing built-in self-test, built-in self-diagnosis and built-in self-repair after the SoC chips are fabricated or during power-on for the SoC chips used for a system. This thesis is a step in meeting this goal.
Dr. Wen-Ben Jone (Advisor)
184 p.
memory; diagnosis; built-in-self-diagnosis; system on chip; embedded memory arrays

Recommended Citations

Citations

  • ARORA, V. (2002). AN EFFICIENT BUILT-IN SELF-DIAGNOSTIC METHOD FOR NON-TRADITIONAL FAULTS OF EMBEDDED MEMORY ARRAYS [Master's thesis, University of Cincinnati]. OhioLINK Electronic Theses and Dissertations Center. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1037998809

    APA Style (7th edition)

  • ARORA, VIKRAM. AN EFFICIENT BUILT-IN SELF-DIAGNOSTIC METHOD FOR NON-TRADITIONAL FAULTS OF EMBEDDED MEMORY ARRAYS. 2002. University of Cincinnati, Master's thesis. OhioLINK Electronic Theses and Dissertations Center, http://rave.ohiolink.edu/etdc/view?acc_num=ucin1037998809.

    MLA Style (8th edition)

  • ARORA, VIKRAM. "AN EFFICIENT BUILT-IN SELF-DIAGNOSTIC METHOD FOR NON-TRADITIONAL FAULTS OF EMBEDDED MEMORY ARRAYS." Master's thesis, University of Cincinnati, 2002. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1037998809

    Chicago Manual of Style (17th edition)

ucin1037998809
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© 2002, all rights reserved.
This open access ETD is published by University of Cincinnati and OhioLINK.