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A BUILT-IN SELF-TESTING METHOD FOR EMBEDDED MULTIPORT MEMORY ARRAYS

NARAYANAN, VINOD A
http://rave.ohiolink.edu/etdc/view?acc_num=ucin1074216619

Abstract Details

2004, MS, University of Cincinnati, Engineering : Electrical Engineering.
With recent advances in semiconductor technologies, the design and use of memories for realizing complex system-on-a-chip (SoC) is very widespread. Semiconductor memories are considered to represent 30-35 percent of the semiconductor market currently. The design flexibility and performance offered by component generators have made the life of the circuit designer easier, but have posted new challenges to test. Thus, testing semiconductor memories efficiently becomes more and more important. Efficient testing schemes for single-port memories are available. Multiport memories are widely used in multi-processor systems, telecommunication ASICs etc. However, little work has been done to use the power of serial interfacing for testing multi-port memories. The proposed method based on the serial interfacing technique has the advantages of high fault coverage, low hardware overhead and tolerable test application time. Precise fault modeling and efficient test design are both important to keep the test cost and test time in acceptable limits.
Dr. Wen-Ben Jone (Advisor)
66 p.
multi-port testing; serial interfacing; memory testing; built-in self test

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Citations

  • NARAYANAN, V. A. (2004). A BUILT-IN SELF-TESTING METHOD FOR EMBEDDED MULTIPORT MEMORY ARRAYS [Master's thesis, University of Cincinnati]. OhioLINK Electronic Theses and Dissertations Center. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1074216619

    APA Style (7th edition)

  • NARAYANAN, VINOD. A BUILT-IN SELF-TESTING METHOD FOR EMBEDDED MULTIPORT MEMORY ARRAYS. 2004. University of Cincinnati, Master's thesis. OhioLINK Electronic Theses and Dissertations Center, http://rave.ohiolink.edu/etdc/view?acc_num=ucin1074216619.

    MLA Style (8th edition)

  • NARAYANAN, VINOD. "A BUILT-IN SELF-TESTING METHOD FOR EMBEDDED MULTIPORT MEMORY ARRAYS." Master's thesis, University of Cincinnati, 2004. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1074216619

    Chicago Manual of Style (17th edition)

ucin1074216619
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© 2004, all rights reserved.
This open access ETD is published by University of Cincinnati and OhioLINK.