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Multi-FPGA Partitioning Using Simulated Annealing

CHEN, TAO
http://rave.ohiolink.edu/etdc/view?acc_num=ucin1077766831

Abstract Details

2004, MS, University of Cincinnati, Engineering : Computer Engineering.
Partitioning becomes necessary when placing a circuit with a large number of gates on chips with area limitation, I/O limitation, or cost consideration. Given the circuit hypergraph, the target architecture and constraints, the partitioning engine divides the design into subsets in a reasonable time so that the cost is optimized. Simulated annealing is a move-based non-deterministic partitioning algorithm. It allows both uphill and downhill moves in order to achieve a global optimum. The core of simulated annealing algorithm is the Metropolis procedure. The simulated annealing partitioning results are controlled by its parameters. In the thesis, the parameters are classified into three categories: temperature-related parameters that control the searching broadness, M-related parameters that control the searching range for each temperature, and threshold parameters that control the acceptance rates. The most difficult part in simulated annealing implementation is to determine the proper parameters for a given hypergraph to make an optimal tradeoff between the result quality and execution time. Circuit topology is introduced to describe the characteristics of the hypergraph. By analyzing some basic parameters, the thesis concludes some common characteristics that lead to determine an optimal implementation schema. PAUSE, a real-world partitioning project, is used in the thesis to reveal how to use simulated annealing for multi-FPGA partitioning in a partitioning environment. Multiple techniques are used to achieve an effective and seamless implementation in PAUSE.
Dr. Ranga Vemuri (Advisor)
116 p.

Recommended Citations

Citations

  • CHEN, T. (2004). Multi-FPGA Partitioning Using Simulated Annealing [Master's thesis, University of Cincinnati]. OhioLINK Electronic Theses and Dissertations Center. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1077766831

    APA Style (7th edition)

  • CHEN, TAO. Multi-FPGA Partitioning Using Simulated Annealing. 2004. University of Cincinnati, Master's thesis. OhioLINK Electronic Theses and Dissertations Center, http://rave.ohiolink.edu/etdc/view?acc_num=ucin1077766831.

    MLA Style (8th edition)

  • CHEN, TAO. "Multi-FPGA Partitioning Using Simulated Annealing." Master's thesis, University of Cincinnati, 2004. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1077766831

    Chicago Manual of Style (17th edition)

ucin1077766831
543
© 2004, all rights reserved.
This open access ETD is published by University of Cincinnati and OhioLINK.