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MODELING AND INTEGRATION OF CONNECTION BLOCK AND MULTI TECHNOLOGY LOGIC CLUSTER WITH ENHANCEMENT FOR THE SECOND GENERATION MT-FPGA

PULIPAKA, PRASHANTH NT
http://rave.ohiolink.edu/etdc/view?acc_num=ucin1155168452

Abstract Details

2006, MS, University of Cincinnati, Engineering : Computer Engineering.
In this age of technological era, the real time applications mandate the design of complex circuits that involve multi-energy domain interaction. While the research till the recent past concentrated only on developing and optimizing such application specific designs, the present day research delved into designing generic multi-domain reconfigurable FPGA with interaction between the digital and analog domains, called the Multi-Technology Field Programmable Gate Array (MT-FPGA). Significant investigation in various design aspects has been explored by doing the layout of the basic architecture. But it is difficult to evaluate the entire architecture, unless fabricated, as the SPICE simulators that perform the timing and functionality check are limited by the complexity of the circuit designed. This involves more cost and time. The other option in evaluating the architecture is by generating the HDL models for the design. With this in place, the design could be thoroughly tested for any size of the architecture. The current thesis involves developing VHDL/VHDL-AMS structural models for two of the major components of the Second Generation MT-FPGA architecture, viz. Multi-Technology Logic Cluster (MTLC) and Connection Block (CB). The delay associated with each of the primary components in the structural design is obtained by performing SPICE simulations on those individual components. The two blocks are then integrated and tested by targeting various applications on to it. The timing results are compared with the ones obtained by testing the chip that contains the combination of these blocks. An enhancement has been made on the carry logic design in the MTLC that allows performing an N-bit arithmetic operation depending on the size of the entire architecture. To get a complete understanding of the functioning of the MT-FPGA, a 1x2 array structure has been developed by instantiating all the essential components of the MT-FPGA viz. MTLC, CB, Switch Block and IO Block. Applications that perform analog to analog communication, digital to digital communication and analog to digital communication
Dr. Fred Beyette (Advisor)
66 p.

Recommended Citations

Citations

  • PULIPAKA, P. N. (2006). MODELING AND INTEGRATION OF CONNECTION BLOCK AND MULTI TECHNOLOGY LOGIC CLUSTER WITH ENHANCEMENT FOR THE SECOND GENERATION MT-FPGA [Master's thesis, University of Cincinnati]. OhioLINK Electronic Theses and Dissertations Center. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1155168452

    APA Style (7th edition)

  • PULIPAKA, PRASHANTH. MODELING AND INTEGRATION OF CONNECTION BLOCK AND MULTI TECHNOLOGY LOGIC CLUSTER WITH ENHANCEMENT FOR THE SECOND GENERATION MT-FPGA. 2006. University of Cincinnati, Master's thesis. OhioLINK Electronic Theses and Dissertations Center, http://rave.ohiolink.edu/etdc/view?acc_num=ucin1155168452.

    MLA Style (8th edition)

  • PULIPAKA, PRASHANTH. "MODELING AND INTEGRATION OF CONNECTION BLOCK AND MULTI TECHNOLOGY LOGIC CLUSTER WITH ENHANCEMENT FOR THE SECOND GENERATION MT-FPGA." Master's thesis, University of Cincinnati, 2006. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1155168452

    Chicago Manual of Style (17th edition)

ucin1155168452
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© 2006, all rights reserved.
This open access ETD is published by University of Cincinnati and OhioLINK.