The continual shrinking of process technologies enables many cores and large caches to be incorporated into future chips. Recent research at Intel suggests that a single chip with hundreds of cores is possible in the near future with the possibility of allocating an entire die for on-chip caches [6]. The ever increasing sizes of on-chip caches and the growing domination of wire delay as the technology shrinks necessitates significant changes to traditional cache architectures. Recently proposed non-uniform cache architectures employ a packet switched on-chip network between banks that yields access times that are a function of where data blocks are found. As the network delay and power are major limiting factors affecting the performance and power of large caches, focus on interconnect network design and its influence on NUCA performance and power is essential.
In this research, we focus on minimizing the latency and power overhead of the network by introducing heterogeneity within the cache inter-bank network. Instead of associating a router to every cache bank as in generic-NoC architectures, we introduce a hybrid-NoC architecture which employs variable number of routers and a shared bus architecture to interconnect NUCA cache banks. Also, by introducing segmentation to a shared bus we are further able to minimize latency and power overhead of the network. CACTI cache simulator is extended to support NUCA modeling with hybrid-NoC topology and its performance and power consumption are analyzed. Network contention plays a non-trivial role in determining the performance of an on-chip network in a CMP environment. We also augment the performance analysis between grid and hybrid topologies with empirical date on network contention, modeled using the multiprocessor simulator GEMS-Ruby. Our simulation results using benchmark programs and the tools such as CACTI and GEMS-Ruby demonstrate that the proposed hybrid-NoC structure has better performance and power consumption over the generic-NoC structure.