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Process Development for ICP Patterning of Through-wafer Periodic Micro-Pores in Silicon Wafers

Jain, Nikhil
http://rave.ohiolink.edu/etdc/view?acc_num=ucin1282328382

Abstract Details

2010, MS, University of Cincinnati, Engineering and Applied Science: Electrical Engineering.
Silicon has been the material of choice in the semiconductor industry since the last 50 years. Silicon etching forms an essential step in the fabrication of micro-electro-mechanical-systems, more commonly known as MEMS devices. Advancements in silicon etching have made possible the era of integrated on-chip sensors. An increase in the feature density is mirrored in the processing power, memory capacity and sensing ability of devices. Through-wafer etching has applications in forming vias for circuits as well as for functioning as interconnects. There is a pressing need for anisotropy in these features. Having a high aspect-ratio is the single most-important requirement for these applications. This prevents us from opting for conventional methods of wet etching which are dependent on the crystal orientation of the wafer and give a big taper. This thesis introduces a technique of fabricating a patterned array of through-wafer micro-holes in silicon wafers using the dry etching technology. Inductively coupled plasma (ICP) etching has emerged as the preferred way of making deep/through-wafer features in silicon wafers as it provides high aspect ratios and much better control over the etch profile as compared to the conventional Reactive ion etching method. A time-multiplexed switched plasma approach is explored for creating vertical sidewall features in the wafers by developing an etch-deposition process. The thesis delves into the intricacies of ICP etching. In the end, possible applications are explored and a particular application involving growth of carbon nanotubes (CNTs) in these holes for making an e-beam device is explained.
Joseph Thomas Boyd, PhD (Committee Chair)
Mark Schulz, PhD (Committee Member)
Robert Jones, PhD (Committee Member)
95 p.
Electrical Engineering
ICP Etching; Plasma Processing of Si; Etch-Dep Process

Recommended Citations

Citations

  • Jain, N. (2010). Process Development for ICP Patterning of Through-wafer Periodic Micro-Pores in Silicon Wafers [Master's thesis, University of Cincinnati]. OhioLINK Electronic Theses and Dissertations Center. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1282328382

    APA Style (7th edition)

  • Jain, Nikhil. Process Development for ICP Patterning of Through-wafer Periodic Micro-Pores in Silicon Wafers. 2010. University of Cincinnati, Master's thesis. OhioLINK Electronic Theses and Dissertations Center, http://rave.ohiolink.edu/etdc/view?acc_num=ucin1282328382.

    MLA Style (8th edition)

  • Jain, Nikhil. "Process Development for ICP Patterning of Through-wafer Periodic Micro-Pores in Silicon Wafers." Master's thesis, University of Cincinnati, 2010. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1282328382

    Chicago Manual of Style (17th edition)

ucin1282328382
702
© 2010, some rights reserved.Creative Commons License Process Development for ICP Patterning of Through-wafer Periodic Micro-Pores in Silicon Wafers by Nikhil Jain is licensed under a Creative Commons Attribution-NonCommercial-NoDerivs 3.0 Unported License. Based on a work at etd.ohiolink.edu.
This open access ETD is published by University of Cincinnati and OhioLINK.