Multi-cores processor architecture has proven to be the solution of diminishing return in processing power when the frequency of uniprocessors is further increased. Because of the bandwidth limit, the current Common Bus communication architecture becomes inefficient if the number of cores in a processor increases more than a handful.New on chip communication architectures has been explored and packet switch Network on Chip has come out to be the future of multi-core interconnects architectures. The performance of the NoC architecture is sensitive to the topology, queue sizes, cache size and its associativity, arbitration scheme, flow control etc. Hence, to study the tradeoffs between area, timing and performance in NoCs is time consuming. The software platform available to run experiments on NoC architectures has many limitations such as
•The time to run benchmarks on the big NoC configurations is huge (in days) making it infeasible to run experiments.
•It does not give accurate information about the cost function such as area, timing and power.
•It does give the feasibility of hardware implementation for these architectures.
The freely available hardware platform tool is very specific for a particular application and does not support re-configurability and detailed simulation.
The proposed Generic Synthesizable HDL (Hardware descriptive platform) Platform for NoCs provides a platform for the multi-core NoC architecture experimentation with the following features:-
•It provides support for Common bus, NoC, hybrid NoCs and hybrid NoC with core migration architectures with customizable parameters such as data width, address width, queue sizes, cache sizes etc.
•Speeds up the simulation if implemented in hardware compared to any software platform.
•Other NoC architectures can be implemented by reusing the components used in the design.
•Gives the accurate estimation of area, timing and performance.
•This can be implemented in any hardware platform such as FPGA, ASIC or Palladium.
•The simulation is more detailed compared to other software or hardware platforms.
•The interface for the design components is generic so that it can be replaced by other application specific components, for example high end processor replacing the processor cores used.
The above platform has been implemented, synthesized and simulated for various NoC configurations.