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8002.pdf (1.8 MB)
ETD Abstract Container
Abstract Header
Fixing Power Bugs at RTL Stage using PSL Assertions
Author Info
Singh, Chandan
Permalink:
http://rave.ohiolink.edu/etdc/view?acc_num=ucin1384426036
Abstract Details
Year and Degree
2013, MS, University of Cincinnati, Engineering and Applied Science: Electrical Engineering.
Abstract
Power dissipation has now become the most critical design constraint. Up till now, in the design flow of any SoC, power estimation and analysis came into the picture only after the completion of RTL synthesis. However, design optimization for low power is most suitable before synthesis. Each decrease in process geometry makes dynamic power targets harder to achieve. Also, changes made later in the design for power optimization lead to costly re-spin. It is better to pin-point power related problems in the design as early as possible when they can still be fixed. It also reduces risk by ensuring that the design meets power goals before embarking on its implementation. A novel approach is presented in this thesis which introduces power analysis at the RTL stage itself using PSL assertions. This will enable the SoC designer to optimize the design from a low power perspective at a very early stage (RTL) in the design flow where the scope of modification is maximized and the cost minimized.
Committee
Carla Purdy, Ph.D. (Committee Chair)
Wen Ben Jone, Ph.D. (Committee Member)
Xuefu Zhou, Ph.D. (Committee Member)
Pages
69 p.
Subject Headings
Electrical Engineering
Keywords
Power Analysis
;
RTL Stage
;
PSL Assertion
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Citations
Singh, C. (2013).
Fixing Power Bugs at RTL Stage using PSL Assertions
[Master's thesis, University of Cincinnati]. OhioLINK Electronic Theses and Dissertations Center. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1384426036
APA Style (7th edition)
Singh, Chandan.
Fixing Power Bugs at RTL Stage using PSL Assertions.
2013. University of Cincinnati, Master's thesis.
OhioLINK Electronic Theses and Dissertations Center
, http://rave.ohiolink.edu/etdc/view?acc_num=ucin1384426036.
MLA Style (8th edition)
Singh, Chandan. "Fixing Power Bugs at RTL Stage using PSL Assertions." Master's thesis, University of Cincinnati, 2013. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1384426036
Chicago Manual of Style (17th edition)
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Document number:
ucin1384426036
Download Count:
510
Copyright Info
© 2013, all rights reserved.
This open access ETD is published by University of Cincinnati and OhioLINK.
Release 3.2.12