Skip to Main Content
 

Global Search Box

 
 
 
 

Files

File List


9179.pdf (1.18 MB)

ETD Abstract Container

Abstract Header

LCPlace: A Novel VLSI Placement Methodology based on large cluster formation

Tirumalai, Nakul
http://rave.ohiolink.edu/etdc/view?acc_num=ucin1396530925

Abstract Details

2014, MS, University of Cincinnati, Engineering and Applied Science: Computer Engineering.
With the fabrication technology approaching 7nm, the number of components to be placed in a digital circuit is increasing rapidly. In this research we explore a new methodology of placement which can work on designs with a large number of cells within a reasonable amount of time. We also show how parallelism can be directly introduced with the new methodology and as a result improve the run-time of the placement process. We evaluate the trade-offs of using the proposed methodology by examining its impact on wirelength, worst-negative slack (WNS) and total negative slack (TNS) generated by placing and routing real designs which have been converted to benchmarks. The key idea is to create large clusters in the netlist at the top level. To place the netlist, the clusters are placed on the placement surface and cells belonging to clusters are placed inside the clusters legally. The cluster boundaries are then collapsed, after which a legalizer is run on the netlist to remove any overlaps occurring among cells, followed by a detailed placer which improves the solution locally. We accomplish the task of clustering and placement of cells within clusters using already available state-of-art academic tools. The analysis of the placement solution is done using Synopsys tools. We record from experimentation that our methodology offers a 5x run-time improvement on an average over all designs which can be improved further by parallelization with an average degradation of 23.6%.
Ranganadha Vemuri, Ph.D. (Committee Chair)
Wen Ben Jone, Ph.D. (Committee Member)
Carla Purdy, Ph.D. (Committee Member)
92 p.
Computer Engineering
VLSI Placement; Large scale clustering

Recommended Citations

Citations

  • Tirumalai, N. (2014). LCPlace: A Novel VLSI Placement Methodology based on large cluster formation [Master's thesis, University of Cincinnati]. OhioLINK Electronic Theses and Dissertations Center. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1396530925

    APA Style (7th edition)

  • Tirumalai, Nakul. LCPlace: A Novel VLSI Placement Methodology based on large cluster formation. 2014. University of Cincinnati, Master's thesis. OhioLINK Electronic Theses and Dissertations Center, http://rave.ohiolink.edu/etdc/view?acc_num=ucin1396530925.

    MLA Style (8th edition)

  • Tirumalai, Nakul. "LCPlace: A Novel VLSI Placement Methodology based on large cluster formation." Master's thesis, University of Cincinnati, 2014. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1396530925

    Chicago Manual of Style (17th edition)

ucin1396530925
414
© 2014, some rights reserved.Creative Commons License LCPlace: A Novel VLSI Placement Methodology based on large cluster formation by Nakul Tirumalai is licensed under a Creative Commons Attribution-NonCommercial-NoDerivs 3.0 Unported License. Based on a work at etd.ohiolink.edu.
This open access ETD is published by University of Cincinnati and OhioLINK.