As semiconductor technology reaches to nanometer scale, the impact of process uncertainties are increasing, leading to performance and power loss, and consequently reducing the yield. These process parameter variations necessitate the use of suitable variation-aware design techniques. There are some architecture level, circuit level, and post silicon techniques with certain overheads to reduce the effect of such variations. Along with good design techniques, variation-aware analysis plays a major role in determining the efficacy of variation tolerant design. Conventional way of min-max static timing analysis is no more a reliable option; we need to use Statistical Static Timing Analysis (SSTA).
Although various techniques for variation tolerant design have been proposed, no major emphasis was given to the initial design phases of the ASIC design flow. In this work, we focused on logic synthesis stage to nullify the effects of process variations. For that, we proposed a novel technique called Library Adaptation for Variation Aware (LAVA) technique and automated the flow for the creation of process variation tolerant design. In LAVA technique a new approach is used to create variation aware libraries by re-characterization of existing libraries and new variation tolerant standard cells are created on demand.
This work proposes a design methodology from RTL to GDSII that incorporates LAVA technique at logic synthesis stage for creating variation tolerant design with negligible overhead. The primary goal of our methodology is to capture the statistical aspects of variation from transistor-level of abstraction into gate-level i.e., standard cell library. This newly created variation-aware standard cell library is provided to the existing logic synthesis tool to select the better design at higher level of design cycle, thus making the design more robust to process variations.
We have used accurate SSTA using PrimeTime VX by providing variation aware libraries and distribution of parameter values. To make the technique more efficient the design is taken to place and route stage using IC Compiler and verified again for the performance in presence of variations.
Results using both combinational and sequential benchmarks clearly show the improvement of critical and near critical paths in presence of process variations with minimal power and area penalty. The use of multi-Vth libraries considerably reduced the power and area overhead introduced by this technique.