Skip to Main Content
 

Global Search Box

 
 
 
 

Files

File List


10418.pdf (869.74 KB)

ETD Abstract Container

Abstract Header

Area Efficient Multi-Ported Memories with Write Conflict Resolution

Muddebihal, Akshata
http://rave.ohiolink.edu/etdc/view?acc_num=ucin1406808833

Abstract Details

2014, MS, University of Cincinnati, Engineering and Applied Science: Electrical Engineering.
Computing systems these days are being designed to take advantage of parallelism in order to increase computational speed. This gives rise to the need for both hardware and software to be designed to achieve as much parallelism as possible. Issue width in the processors is being increased to support Instruction Level Parallelism. To gain performance increase from this, corresponding changes have to be made in the processor architecture as well. Wide issue machines like superscalar processors require an increase in the number of ports in the data path memory. In this thesis we focus on enhancing parallelism in memory by making it multi-ported. FPGAs offer an attractive platform to build multi-ported memories. They have dual ported embedded memory blocks of fixed number and size which can be used as building blocks for memories with more ports. Various authors previously have constructed multi-ported memory with an arbitrary number of ports using the Live Value Table (LVT) technique. In this work, we build better memories in terms of area by modifying the LVT technique. As an example, we build a 32-bit wide, 256-bit deep 4W/8R memory which consumes 43% fewer logic elements and 75% fewer block RAMs as compared to the original LVT technique. The effect of different write port-to-read port ratios is studied apart from the common case where read ports are double the number of write ports. We also add an extra feature to memory. A write conflict detection and resolution circuit is built entirely in hardware to relieve the software programmer of the task of scheduling the writes using software. Two designs for this circuit are implemented and compared.
Carla Purdy, Ph.D. (Committee Chair)
Wen Ben Jone, Ph.D. (Committee Member)
George Purdy, Ph.D. (Committee Member)
74 p.
Engineering
Multi-ported memory; Live Value Table; FPGA; write conflict resolution; area reduction

Recommended Citations

Citations

  • Muddebihal, A. (2014). Area Efficient Multi-Ported Memories with Write Conflict Resolution [Master's thesis, University of Cincinnati]. OhioLINK Electronic Theses and Dissertations Center. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1406808833

    APA Style (7th edition)

  • Muddebihal, Akshata. Area Efficient Multi-Ported Memories with Write Conflict Resolution. 2014. University of Cincinnati, Master's thesis. OhioLINK Electronic Theses and Dissertations Center, http://rave.ohiolink.edu/etdc/view?acc_num=ucin1406808833.

    MLA Style (8th edition)

  • Muddebihal, Akshata. "Area Efficient Multi-Ported Memories with Write Conflict Resolution." Master's thesis, University of Cincinnati, 2014. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1406808833

    Chicago Manual of Style (17th edition)

ucin1406808833
1,124
© 2014, all rights reserved.
This open access ETD is published by University of Cincinnati and OhioLINK.