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FPGA-based fault tolerant design and deterministic routing-based synthesis for Digital Microfluidic Biochips

Todakar, Onkar
http://rave.ohiolink.edu/etdc/view?acc_num=ucin1447071424

Abstract Details

2015, MS, University of Cincinnati, Engineering and Applied Science: Computer Engineering.
Microfluidic biochips have been widely used as an alternative to traditional laboratory equipment. They offer a considerable advantage over traditional equipment when the reduction in cost, area and efforts is considered. A lot of research has been done on designing general purpose, cost-effective architectures and also on methods to automate the mapping of assays on to these biochips. Biochips are susceptible to failures due to various reasons such as manufacturing defects, wear and tear etc. We propose a fault tolerant scheduling algorithm which reconfigures the DMFBs in the presence of such faults. A faulty module (for example a mixer with 2x5 electrodes) can be reconfigured using a droplet routing approach that routes droplet, avoiding the faulty electrodes. We observe an average 23% reduction in the assay completion time, when compared to a DMFB with a faulty module. We further extend this routing-based approach to propose an algorithm to map assays to DMFBs. Most of the previous work on mapping assays assumes the presence of virtual modules on DMFBs and schedules operations on them. In our work we propose a deterministic greedy algorithm that routes the droplet on a random sequence of electrodes rather than restricting it to a virtual module to execute the operation. Our algorithm moves the droplets on the DMFB such that the operation is completed in the minimum possible time. The results show approximately 43% reduction in assay completion time, when compared to traditional module based mapping algorithm on a FPGA style DMFB array, and 26% improvement compared to the randomized routing - based synthesis algorithm GRASP.
Wen-Ben Jone, Ph.D. (Committee Chair)
Rashmi Jha, Ph.D. (Committee Member)
Ian Papautsky, Ph.D. (Committee Member)
71 p.
Engineering
Routing-based synthesis; DMFBs; Fault-tolerant

Recommended Citations

Citations

  • Todakar, O. (2015). FPGA-based fault tolerant design and deterministic routing-based synthesis for Digital Microfluidic Biochips [Master's thesis, University of Cincinnati]. OhioLINK Electronic Theses and Dissertations Center. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1447071424

    APA Style (7th edition)

  • Todakar, Onkar. FPGA-based fault tolerant design and deterministic routing-based synthesis for Digital Microfluidic Biochips. 2015. University of Cincinnati, Master's thesis. OhioLINK Electronic Theses and Dissertations Center, http://rave.ohiolink.edu/etdc/view?acc_num=ucin1447071424.

    MLA Style (8th edition)

  • Todakar, Onkar. "FPGA-based fault tolerant design and deterministic routing-based synthesis for Digital Microfluidic Biochips." Master's thesis, University of Cincinnati, 2015. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1447071424

    Chicago Manual of Style (17th edition)

ucin1447071424
389
© 2015, some rights reserved.Creative Commons License FPGA-based fault tolerant design and deterministic routing-based synthesis for Digital Microfluidic Biochips by Onkar Todakar is licensed under a Creative Commons Attribution-NonCommercial-NoDerivs 3.0 Unported License. Based on a work at etd.ohiolink.edu.
This open access ETD is published by University of Cincinnati and OhioLINK.