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A Verilog Description and Efficient Hardware Implementation of the Baillie-PSW Primality Test

Kasarabada, Yasaswy
http://rave.ohiolink.edu/etdc/view?acc_num=ucin1471347471

Abstract Details

2016, MS, University of Cincinnati, Engineering and Applied Science: Computer Engineering.
Prime numbers have been an important topic of study among mathematicians. With the increasing usage of large primes in major cryptographic algorithms like RSA and Diffie-Hellman Key Exchange, the study and method of generation of primes have gained much significance in information security. For a long period of time, generation of primes in software was common practice. However, in recent years, citing confidence and security, prime number generation in hardware is being considered as an alternative. Considering time complexity and hardware implementation issues, probabilistic primality tests are preferred over deterministic tests. The Baillie-PSW primality test is a strong probabilistic primality test, as no known Baillie-PSW pseudoprime exists. In this thesis, we briefly discuss the different types of cryptographic algorithms and primality tests. We also study a few hardware implementations of some of the primality algorithms, namely the Miller-Rabin and Lucas tests. Our work concentrates on the implementation of a Verilog-based design of the Baillie-PSW primality test on an Altera Cyclone IV GX FPGA. To our knowledge, this is the first hardware implementation of this primality test. The implementation takes in an odd random number as input and returns the next immediate probable prime number. Numbers that are 1024 bits wide are preferred for their use in modern cryptographic algorithms. The results from our implementation are analyzed and methods to improve the results are discussed.
Carla Purdy, Ph.D. (Committee Chair)
Wen-Ben Jone, Ph.D. (Committee Member)
George Purdy, Ph.D. (Committee Member)
101 p.
Computer Engineering
Baillie-PSW test; hardware implementation; Verilog; FPGA; Cyclone IV GX

Recommended Citations

Citations

  • Kasarabada, Y. (2016). A Verilog Description and Efficient Hardware Implementation of the Baillie-PSW Primality Test [Master's thesis, University of Cincinnati]. OhioLINK Electronic Theses and Dissertations Center. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1471347471

    APA Style (7th edition)

  • Kasarabada, Yasaswy. A Verilog Description and Efficient Hardware Implementation of the Baillie-PSW Primality Test. 2016. University of Cincinnati, Master's thesis. OhioLINK Electronic Theses and Dissertations Center, http://rave.ohiolink.edu/etdc/view?acc_num=ucin1471347471.

    MLA Style (8th edition)

  • Kasarabada, Yasaswy. "A Verilog Description and Efficient Hardware Implementation of the Baillie-PSW Primality Test." Master's thesis, University of Cincinnati, 2016. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1471347471

    Chicago Manual of Style (17th edition)

ucin1471347471
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© 2016, all rights reserved.
This open access ETD is published by University of Cincinnati and OhioLINK.
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