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Reverse Engineering of Finite State Machines from Sequential Circuits

Vamja, Harsh
http://rave.ohiolink.edu/etdc/view?acc_num=ucin1530267556456191

Abstract Details

2018, MS, University of Cincinnati, Engineering and Applied Science: Computer Engineering.
For many years, reverse engineering of hardware designs has been an area of great interest. Efficient and structured analysis of fabricated designs is important for several reasons, such as design validation, IP protection, process quality control etc. More recently, multivariate nature of semiconductor supply-chain has opened doors for insertion of obscure hardware vulnerabilities making hardware integrity check essential for ICs used in critical application areas. Most traditional hardware reverse engineering techniques are invasive and lead to a partial or complete destruction of the system under investigation which is often times unwanted. In this thesis, we present scalable, non-invasive procedures to reverse engineer unknown CMOS based ICs. Specifically, the focus is on black-box analysis of unknown Moore Finite State Machine based sequential circuit designs. We present two different recovery techniques based on a novel analysis approach that combines investigation of input-output responses and power consumption of the system under investigation. The first technique performs a tree-based guided exploration of the machine structure and employs subtree matching to identify distinct and equivalent states. The second technique translates machine exploration and state identification into a constraint satisfaction problem that can be efficiently handled by a SMT Solver. The advantage of the tree-based approach is that it guarantees a minimally equivalent recovery, whereas the solver-based approach works adaptively and hence, faster and scalable to handle large machines. Both these techniques successfully recover a logically equivalent state machine structure. To study the efficiency and performance of the proposed techniques we present its implementation. We compare the execution times for different standard MCNC benchmark machines and show that the solver-based recovery technique is faster.
Ranganadha Vemuri, Ph.D. (Committee Chair)
Wen-Ben Jone, Ph.D. (Committee Member)
Carla Purdy, Ph.D. (Committee Member)
127 p.
Computer Engineering
Reverse Engineering; Finite State Machines; Hardware Security; Non-invasive Analysis; Sequential Circuits; Black-box Analysis

Recommended Citations

Citations

  • Vamja, H. (2018). Reverse Engineering of Finite State Machines from Sequential Circuits [Master's thesis, University of Cincinnati]. OhioLINK Electronic Theses and Dissertations Center. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1530267556456191

    APA Style (7th edition)

  • Vamja, Harsh. Reverse Engineering of Finite State Machines from Sequential Circuits. 2018. University of Cincinnati, Master's thesis. OhioLINK Electronic Theses and Dissertations Center, http://rave.ohiolink.edu/etdc/view?acc_num=ucin1530267556456191.

    MLA Style (8th edition)

  • Vamja, Harsh. "Reverse Engineering of Finite State Machines from Sequential Circuits." Master's thesis, University of Cincinnati, 2018. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1530267556456191

    Chicago Manual of Style (17th edition)

ucin1530267556456191
427
© 2018, all rights reserved.
This open access ETD is published by University of Cincinnati and OhioLINK.