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Security Architecture and Dynamic Signal Selection for Post-Silicon Validation

Raja, Subashree
http://orcid.org/0000-0002-4690-9805
http://rave.ohiolink.edu/etdc/view?acc_num=ucin1623241837129969

Abstract Details

2021, MS, University of Cincinnati, Engineering and Applied Science: Computer Engineering.
The increasing complexity of the System-on-chip (SoC) design due to the reuse of third-party Intellectual Property (IP) cores hinders testing all the corner cases and detecting hard-to-find bugs before fabrication. To detect the malfunctioning of SoC designs, many verification techniques have been proposed over the years. SoC security policies help to find bugs by providing a set of safeguards against unauthorized access [1] of the design. Post-silicon validation helps in monitoring the security policies after the prototype fabrication. Trace buffer-based techniques have been widely used for real-time data acquisition in post-silicon validation. Trace buffers increase the visibility of the circuit while emphasizing the importance of continuous data sampling in the detection of bugs. The two major aspects of trace buffer-based debugging are trace signal selection and signal restoration. The process of selecting a set of internal signals for tracing is called trace signal selection. The signal restoration helps in finding the values of untraced signals using the selected signals data. Many researchers have focused on improving the restoration by employing various signal selection techniques to localize the errors in the circuit. However, most of these techniques assume a uniform distribution of errors across the circuit while in reality, the distribution is irregular. Post-silicon validation also poses a major challenge due to its limited controllability and observability of the SoC as only a small subset of signals can be chosen for tracing for a small area trade-off. Validation and enforcement of security policies after fabrication and during run-time pose an additional challenge. The aforementioned limitations and disadvantages can be overcome by using our post-silicon validation method with a minimum area and power overhead. In this research, we propose a methodology for post-silicon validation through the evaluation of security assertions for systems-on-chip (SoC). The methodology is centered around a security architecture in which a "security capsule" is attached to each IP core in the SoC. The security capsule consists of a set of on-line and off-line assertion monitors, a dynamic trace-buffer to trace selected groups of signals, and a dynamic trace controller. The architecture is supported by a trace signal selection and grouping algorithm and a dynamic signal tracing method to evaluate the off-chip monitors. This paper presents the security capsule architecture, the signal selection, and grouping algorithm, and the run-time signal tracing method. Results of using the methodology on two SoC architectures based on the OpenRISC-1200 and RISC-V processors are presented.
Ranganadha Vemuri, Ph.D. (Committee Chair)
Wen-Ben Jone, Ph.D. (Committee Member)
Carla Purdy, Ph.D. (Committee Member)
84 p.
Computer Engineering
Post-silicon validation; Trace buffer; Dynamic signal selection; System-on-Chip; Run-time security monitors

Recommended Citations

Citations

  • Raja, S. (2021). Security Architecture and Dynamic Signal Selection for Post-Silicon Validation [Master's thesis, University of Cincinnati]. OhioLINK Electronic Theses and Dissertations Center. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1623241837129969

    APA Style (7th edition)

  • Raja, Subashree. Security Architecture and Dynamic Signal Selection for Post-Silicon Validation. 2021. University of Cincinnati, Master's thesis. OhioLINK Electronic Theses and Dissertations Center, http://rave.ohiolink.edu/etdc/view?acc_num=ucin1623241837129969.

    MLA Style (8th edition)

  • Raja, Subashree. "Security Architecture and Dynamic Signal Selection for Post-Silicon Validation." Master's thesis, University of Cincinnati, 2021. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1623241837129969

    Chicago Manual of Style (17th edition)

ucin1623241837129969
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This open access ETD is published by University of Cincinnati and OhioLINK.