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Critical DATAPATH Cells for NCL Asynchronous Circuit Area Reduction

Phillips, Dallas
http://orcid.org/0000-0003-2086-225X
http://rave.ohiolink.edu/etdc/view?acc_num=ucin1649763550480561

Abstract Details

2022, MS, University of Cincinnati, Engineering and Applied Science: Electrical Engineering.
At the heart of the chip design industry are synchronous combinational circuits that perform all sorts of mathematical and Boolean operations in high level systems. For proprietary IC designs, the lack of security for those designs proposes potential leaks of sensitive information particularly via side channel attacks (SCA). Asynchronously designed circuits inherently have better security features but compromise significant area to implement compared to their synchronous counterparts. We propose a new way of designing circuits, with NCL-based logic gate designs that are able to process synchronous and asynchronous signals simultaneously. By converting specific critical paths of a synchronous netlist using these originally designed hybrid gates we call DATAPATH gates, less area is consumed (only a 7.7\% area increase from fully combinational version in this case) while the security benefits from asynchronous logic is added to the system. These critical paths then are able to function asynchronously while still maintaining the original functionality and timing information.
John Emmert, Ph.D. (Committee Member)
Ranganadha Vemuri, Ph.D. (Committee Member)
Wen-Ben Jone, Ph.D. (Committee Member)
57 p.
Electrical Engineering
asynchronous; combinational logic; hybrid circuitry; path conversion; side-channel analysis; null convention logic

Recommended Citations

Citations

  • Phillips, D. (2022). Critical DATAPATH Cells for NCL Asynchronous Circuit Area Reduction [Master's thesis, University of Cincinnati]. OhioLINK Electronic Theses and Dissertations Center. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1649763550480561

    APA Style (7th edition)

  • Phillips, Dallas. Critical DATAPATH Cells for NCL Asynchronous Circuit Area Reduction. 2022. University of Cincinnati, Master's thesis. OhioLINK Electronic Theses and Dissertations Center, http://rave.ohiolink.edu/etdc/view?acc_num=ucin1649763550480561.

    MLA Style (8th edition)

  • Phillips, Dallas. "Critical DATAPATH Cells for NCL Asynchronous Circuit Area Reduction." Master's thesis, University of Cincinnati, 2022. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1649763550480561

    Chicago Manual of Style (17th edition)

ucin1649763550480561
74
© 2022, some rights reserved.Creative Commons License Critical DATAPATH Cells for NCL Asynchronous Circuit Area Reduction by Dallas Phillips is licensed under a Creative Commons Attribution-NonCommercial-NoDerivs 3.0 Unported License. Based on a work at etd.ohiolink.edu.
This open access ETD is published by University of Cincinnati and OhioLINK.