Skip to Main Content
 

Global Search Box

 
 
 
 

Files

File List


ucin982010436.pdf (909.06 KB)

ETD Abstract Container

Abstract Header

COMPILER OPTIMIZATIONS FOR POWER ON HIGH PERFORMANCE PROCESSORS

RELE, SIDDHARTH N
http://rave.ohiolink.edu/etdc/view?acc_num=ucin982010436

Abstract Details

2001, MS, University of Cincinnati, Engineering : Computer Science and Engineering.
The performance and the computing power of the processors is growingat a phenomenal rate leading to increased power dissipation and hence lower battery life. There are some initiatives being undertaken in this area to decrease the power requirements of processors, using hardware and software mechanisms. In our work, we try to investigate a software technique to reduce power consumption in high performance processors with multiple functional units. The leakage current, which leads to static power is becoming an increasingly important part of the power dissipation.We try to reduce this leakage static power through software mechanisms by switching OFF the idle units. This reduction is obtained by identifying those units which will be left idle for a long time in the execution path and generating instructions to switch OFF such units. We generate power efficient code using a two pass compiler framework. The first pass builds the Power aware control flow graph, which is a control flow graph annotated with profiling information and processor configuration required for each block. The second pass compares the configuration of all the blocks in the control flow graph with its successors to generate the power efficient code. Code to switch ON/OFF functional units are generated on the paths with low execution frequency. The code generated by our compiler is simulated by a MIPS simulator generated using UPFAST system, an automatic cycle level simulator. The simulator simulates a novel Instruction Set Architecture termed as Power Aware MIPS [PAwMIPS], which is an extension of the MIPS-I instruction set. Since power optimizations usually target the dynamic power component, these methods might have an adverse effect on the performance of the system. We deal with the static power component and quantify power in terms of number of OFF functional units. Our optimizations result in reduction of about 90% in static power consumption for some of the units of the processor, with a very minimal performance degradation i.e under 1% in most of the cases.
Dr. Santosh Pande (Advisor)
79 p.
Computer Science
power optimizations; power savings; software techniques; static power; leakage power

Recommended Citations

Citations

  • RELE, S. N. (2001). COMPILER OPTIMIZATIONS FOR POWER ON HIGH PERFORMANCE PROCESSORS [Master's thesis, University of Cincinnati]. OhioLINK Electronic Theses and Dissertations Center. http://rave.ohiolink.edu/etdc/view?acc_num=ucin982010436

    APA Style (7th edition)

  • RELE, SIDDHARTH. COMPILER OPTIMIZATIONS FOR POWER ON HIGH PERFORMANCE PROCESSORS. 2001. University of Cincinnati, Master's thesis. OhioLINK Electronic Theses and Dissertations Center, http://rave.ohiolink.edu/etdc/view?acc_num=ucin982010436.

    MLA Style (8th edition)

  • RELE, SIDDHARTH. "COMPILER OPTIMIZATIONS FOR POWER ON HIGH PERFORMANCE PROCESSORS." Master's thesis, University of Cincinnati, 2001. http://rave.ohiolink.edu/etdc/view?acc_num=ucin982010436

    Chicago Manual of Style (17th edition)

ucin982010436
715
© 2001, all rights reserved.
This open access ETD is published by University of Cincinnati and OhioLINK.