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MEMORY SYNTHESIS FOR FPGA-BASED RECONFIGURABLE COMPUTERS

KASAT, AMIT
http://rave.ohiolink.edu/etdc/view?acc_num=ucin988222220

Abstract Details

2001, MS, University of Cincinnati, Engineering : Computer Engineering.
A design executing on Reconfigurable Computer (RC) typically reads from and writes to physical memories on the RC. For data intensive applications like Digital Signal Processing (DSP), Image Processing, Pattern Recognition, etc. memory reads and writes constitute a large portion of the total design execution time. With the advent of on-chip memories available on various FPGA devices, a complete hierarchy of physical memories is now available on a RC. Different types of memories provide different access latencies, storage capacities, multiple ports etc. An intelligent usage of these memories can lead to significant improvement in the read/write latency of the design. Most automated synthesis tools targeted for RCs do a trivial form of memory mapping, which does not make use of this memory hierarchy. In order to exploit the memory hierarchy, more sophisticated logic partitioning and memory mapping tools arerequired. This thesis presents an automated memory mapping methodology during high level synthesis flow. By memory mapping, we mean performing a detailed assignment of various data structures, which are part of thedesign, to the physical memories available on the RC. We use TabuSearch meta-heuristic to find a good mapping for various logical memories of the design onto physical memories available on the RC. We present a heuristic, called Rectangle Carving, to map a single logical memory onto the RC. Tabu search calls this heuristic at every iteration to get new solutions. To ensure correct functionality for the memory mapping, additional control logic is required. This logic is used to resolve potential memory access conflicts, and to make the details of memory mapping transparent to the accessing logic, thus keeping the implementation of the logic independent of memory mapping. Quality of memory mapping is closely related to the way logic partitioning is done on the board. We present an integrated methodology to perform both logic partitioning and memory mapping together. A tabu search formulation is used to do the task. This helps in getting good overall design mapping in very little time. The execution time of the tool on benchmark examples is found to be very small. For design containing 100 logical memories, the stand alone memory mapper took less than 150 seconds. The heuristic is produces results within 3.5 % of the near optimal results produced by the ILP-approach. The spatial partitioner took less than 800 seconds for designs having 100 compute tasks and 100 logical memories.
Dr. Ranga Vemuri (Advisor)
79 p.
FPGA; Memory Synthesis; On-chip RAM; Reconfigurable computers; Logic partitioning

Recommended Citations

Citations

  • KASAT, A. (2001). MEMORY SYNTHESIS FOR FPGA-BASED RECONFIGURABLE COMPUTERS [Master's thesis, University of Cincinnati]. OhioLINK Electronic Theses and Dissertations Center. http://rave.ohiolink.edu/etdc/view?acc_num=ucin988222220

    APA Style (7th edition)

  • KASAT, AMIT. MEMORY SYNTHESIS FOR FPGA-BASED RECONFIGURABLE COMPUTERS. 2001. University of Cincinnati, Master's thesis. OhioLINK Electronic Theses and Dissertations Center, http://rave.ohiolink.edu/etdc/view?acc_num=ucin988222220.

    MLA Style (8th edition)

  • KASAT, AMIT. "MEMORY SYNTHESIS FOR FPGA-BASED RECONFIGURABLE COMPUTERS." Master's thesis, University of Cincinnati, 2001. http://rave.ohiolink.edu/etdc/view?acc_num=ucin988222220

    Chicago Manual of Style (17th edition)

ucin988222220
917
© 2001, all rights reserved.
This open access ETD is published by University of Cincinnati and OhioLINK.