Digital Radio Frequency Memories (DRFM) are widely used as modules in digital signal processing. These modules can provide several forms of signal manipulation and storage capabilities. With single event effects caused by environmental radiation the need for a radiation hardened DRFM is increased. Typical radiation hardening involves the use of specialized foundries utilizing proprietary CMOS libraries that are expensive to build or adding lead packages around a chip that is expensive and add weight to the chip. An alternative radiation hardening technique is to utilize a radiation hardened by design library. This library includes digital gates that have been hardened by the use of guard rings, reverse body bias or other methods. With the use of the hardened library, commercial synthesis tools can create a structural Verilog output from the behavioral VHDL design. The radiation hardened by design circuit will be larger than a non-hardened design, but can be fabricated using standard foundries.
This research also takes advantage of current advancements of commercially available software and designs that have led to a structured ASIC approach for fabricating a design. This structured ASIC approach fabricates a design in two stages. The first stage is the transistor and bottom metal layers with the second stage being the top metal layers. Silicon wafers can be fabricated in bulk using the first stage of uncommitted logic with separate top metal layer masks applied to commit the logic to a specific design. A radiation hardened by design standard cell library was used to create the Structured ASIC standard cells and will allow production of radiation hardened circuits with a short design time.
For this research, a generic frequency shifting DSSM is proposed that targets a radiation hardened by design Structured ASIC to deliver performance in processing as well as radiation hardening at both the transistor level and gate level. This research produces a parameterizable DSSM VHDL design that can be easily modified to produce a DSSM with various signal processing and storage capabilities with minimal modifications. The designed DSSM was tested on an FPGA board for prototyping, but was ultimately targeted for the radiation hardened by design structured ASIC. The design created through this research was compared to a non-hardened DSSM using a similar CMOS process for area, power, speed and Spur Free Dynamic Range.