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High-frequency wide-range all digital phase locked loop in 90nm CMOS

Muppala, Prashanth
http://rave.ohiolink.edu/etdc/view?acc_num=wright1313551049

Abstract Details

2011, Master of Science in Engineering (MSEgr), Wright State University, Electrical Engineering.
This thesis presents a high-frequency wide tuning range all digital phase locked loop (ADPLL) in 90 nm CMOS process with 1.2 V power supply. It operates in the frequency range of 2-7.2 GHz with wide linearity and high resolution. The ADPLL uses a wide frequency range digital controlled oscillator (DCO) and averaging technique to obtain fast lock time. The operation of the ADPLL includes both a frequency acquisition state and a phase acquisition state. A novel architecture is implemented in a coarse stage to obtain a monotonically increasing wide frequency range DCO for frequency acquisition and a fine control stage is used to achieve resolution of 0.1 MHz for phase tracking and maintenance. Design considerations of the ADPLL circuit components and implementation using Cadence tools are presented. Spectre simulations demonstrate a significant improvement compared to recent architectures with 15 ps of peak-peak jitter and a root mean square value of 4 ps when locked at 5.12 GHz. The power consumption at 5.12 GHz is 5 mW and the locking time is 3.5 μs.
Saiyu Ren, PhD (Advisor)
Raymond Siferd, PhD (Committee Member)
Henry Chen, PhD (Committee Member)
71 p.
Electrical Engineering
all digital phase locked loop; ADPLL; CMOS

Recommended Citations

Citations

  • Muppala, P. (2011). High-frequency wide-range all digital phase locked loop in 90nm CMOS [Master's thesis, Wright State University]. OhioLINK Electronic Theses and Dissertations Center. http://rave.ohiolink.edu/etdc/view?acc_num=wright1313551049

    APA Style (7th edition)

  • Muppala, Prashanth. High-frequency wide-range all digital phase locked loop in 90nm CMOS. 2011. Wright State University, Master's thesis. OhioLINK Electronic Theses and Dissertations Center, http://rave.ohiolink.edu/etdc/view?acc_num=wright1313551049.

    MLA Style (8th edition)

  • Muppala, Prashanth. "High-frequency wide-range all digital phase locked loop in 90nm CMOS." Master's thesis, Wright State University, 2011. http://rave.ohiolink.edu/etdc/view?acc_num=wright1313551049

    Chicago Manual of Style (17th edition)

wright1313551049
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© 2011, all rights reserved.
This open access ETD is published by Wright State University and OhioLINK.