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Timing and Power Optimization Using Mixed-Dynamic-Static CMOS

Xue, Hao
http://rave.ohiolink.edu/etdc/view?acc_num=wright1377131599

Abstract Details

2013, Master of Science in Engineering (MSEgr), Wright State University, Electrical Engineering.
An effective approach to timing and power optimization for single clocking and multiple clocking dynamic CMOS designs is presented in this thesis. For the single-clocking scheme dynamic CMOS sub-blocks can be replaced by static CMOS and mixed-dynamic-static CMOS for power minimization. For the multiple-clocking scheme the delay of data ready for use plays more important role than its clock pulse in timing optimization. Power minimization can be achieved by implementing dynamic CMOS sub-blocks with static or mixed-dynamic-static CMOS. In comparison with the benchmark 16-bit carry select adder in dynamic CMOS, the critical path delay is reduced by 41.1% using the single-clock optimization approach; the power and delay are reduced by 43% and 41.1% respectively using the multiple-clock optimization approach. In comparison with the benchmark 64-bit comparator in dynamic CMOS, the critical path delay is reduced by 49% using the single-clock optimization approach; the power and delay are reduced by 43.1% and 49% respectively using the multiple-clock optimization approach.
Henry Chen, Ph.D. (Advisor)
Saiyu Ren, Ph.D. (Committee Member)
Yan Zhuang, Ph.D. (Committee Member)
60 p.
Electrical Engineering

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Citations

  • Xue, H. (2013). Timing and Power Optimization Using Mixed-Dynamic-Static CMOS [Master's thesis, Wright State University]. OhioLINK Electronic Theses and Dissertations Center. http://rave.ohiolink.edu/etdc/view?acc_num=wright1377131599

    APA Style (7th edition)

  • Xue, Hao. Timing and Power Optimization Using Mixed-Dynamic-Static CMOS. 2013. Wright State University, Master's thesis. OhioLINK Electronic Theses and Dissertations Center, http://rave.ohiolink.edu/etdc/view?acc_num=wright1377131599.

    MLA Style (8th edition)

  • Xue, Hao. "Timing and Power Optimization Using Mixed-Dynamic-Static CMOS." Master's thesis, Wright State University, 2013. http://rave.ohiolink.edu/etdc/view?acc_num=wright1377131599

    Chicago Manual of Style (17th edition)

wright1377131599
486
© 2013, some rights reserved.Creative Commons License Timing and Power Optimization Using Mixed-Dynamic-Static CMOS by Hao Xue is licensed under a Creative Commons Attribution-NonCommercial-NoDerivs 3.0 Unported License. Based on a work at etd.ohiolink.edu.
This open access ETD is published by Wright State University and OhioLINK.