Skip to Main Content
Frequently Asked Questions
Submit an ETD
Global Search Box
Need Help?
Keyword Search
Participating Institutions
Advanced Search
School Logo
Files
File List
Anvesh_Thesis.pdf (613.14 KB)
ETD Abstract Container
Abstract Header
A Genetic Algorithm for ASIC Floorplanning
Author Info
Perumalla, Anvesh Kumar
ORCID® Identifier
http://orcid.org/0000-0003-3403-8907
Permalink:
http://rave.ohiolink.edu/etdc/view?acc_num=wright1484236480221006
Abstract Details
Year and Degree
2016, Master of Science in Electrical Engineering (MSEE), Wright State University, Electrical Engineering.
Abstract
Semiconductor integrated circuits (ICs) have become key components in almost every aspect of our daily lives. From simple home appliances to extremely sophisticated aerospace systems, we have become increasingly dependent on ICs. System-on-chip (SoC) is an IC methodology that includes multiple design technologies on a single IC chip. SoC was developed to further integrate and manage system complexity. Due to SoC and increasingly dense IC fabrication technologies, design time and thereby system time-to-market are becoming more critical drivers of the IC design cycle. In order to address issues related to design time and time-to-market, highly optimized semiconductor intellectual property (IP) is often leveraged. These IP blocks are predesigned, highly optimized sub-system components. To take full advantage of these and other sub-components, we have developed a Genetic Algorithm (Simulated Evolution) based floorplanning tool to quickly and efficiently solve the SoC and application specific integrated circuit (ASIC) floorplanning problem. Our tool takes advantage of both hard and soft macros to optimize IC area usage.
Committee
John Marty Emmert, Ph.D. (Advisor)
Raymond Siferd, Ph.D. (Committee Member)
Saiyu Ren, Ph.D. (Committee Member)
Pages
50 p.
Subject Headings
Electrical Engineering
Keywords
ASIC
;
Floorplan
;
Genetic Algorithm
;
Simulated Evolution
;
SoC
Recommended Citations
Refworks
EndNote
RIS
Mendeley
Citations
Perumalla, A. K. (2016).
A Genetic Algorithm for ASIC Floorplanning
[Master's thesis, Wright State University]. OhioLINK Electronic Theses and Dissertations Center. http://rave.ohiolink.edu/etdc/view?acc_num=wright1484236480221006
APA Style (7th edition)
Perumalla, Anvesh.
A Genetic Algorithm for ASIC Floorplanning.
2016. Wright State University, Master's thesis.
OhioLINK Electronic Theses and Dissertations Center
, http://rave.ohiolink.edu/etdc/view?acc_num=wright1484236480221006.
MLA Style (8th edition)
Perumalla, Anvesh. "A Genetic Algorithm for ASIC Floorplanning." Master's thesis, Wright State University, 2016. http://rave.ohiolink.edu/etdc/view?acc_num=wright1484236480221006
Chicago Manual of Style (17th edition)
Abstract Footer
Document number:
wright1484236480221006
Download Count:
1,357
Copyright Info
© 2016, some rights reserved.
A Genetic Algorithm for ASIC Floorplanning by Anvesh Kumar Perumalla is licensed under a Creative Commons Attribution-NonCommercial-ShareAlike 3.0 Unported License. Based on a work at etd.ohiolink.edu.
This open access ETD is published by Wright State University and OhioLINK.