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Implementation of High Speed and Low Power Radix-4 8*8 Booth Multiplier in CMOS 32nm Technology

Patel, Rishit Navinbhai
http://rave.ohiolink.edu/etdc/view?acc_num=wright1495371138748713

Abstract Details

2017, Master of Science in Electrical Engineering (MSEE), Wright State University, Electrical Engineering.
According to Moore’s law, number of transistors integrated on a single chip double every 18 months with a lot new functionality embedded, which results the increasing of delay and power consumption of a chip. To improve the performance of a more complicated digital circuit design, faster and power efficient digital sub-components are in urgent need. Multipliers are the key components in the field of DSP, GPU and CPU which compute enormous amount of binary data. A radix-4 8*8 booth multiplier is proposed and implemented in this thesis aiming to reduce power delay product. Four stages with different architecture are used to implement this multiplier rather than traditional 8*8 booth multiplier. Instead of using adder in stage-1, it is replaced with binary-to-access one converter circuit and 10-bit MUX 2:1 to reduce power consumption by 23.76% and increase speed by 12.02% compared to stage-1 of traditional 8*8 booth multiplier. This proposed design is implemented in CMOS 32nm technology at 1.0 voltage supply. The worst-case delay of the proposed radix-4 8*8 booth multiplier at 2 Giga data rate is 423 picosecond and power consumption of 0.274 milli-watts with transistor count of 2860.
Saiyu Ren, Ph.D. (Advisor)
Ray Siferd, Ph.D. (Committee Member)
Jiafeng Xie , Ph.D. (Committee Member)
67 p.
Electrical Engineering
electrical engineering

Recommended Citations

Citations

  • Patel, R. N. (2017). Implementation of High Speed and Low Power Radix-4 8*8 Booth Multiplier in CMOS 32nm Technology [Master's thesis, Wright State University]. OhioLINK Electronic Theses and Dissertations Center. http://rave.ohiolink.edu/etdc/view?acc_num=wright1495371138748713

    APA Style (7th edition)

  • Patel, Rishit. Implementation of High Speed and Low Power Radix-4 8*8 Booth Multiplier in CMOS 32nm Technology . 2017. Wright State University, Master's thesis. OhioLINK Electronic Theses and Dissertations Center, http://rave.ohiolink.edu/etdc/view?acc_num=wright1495371138748713.

    MLA Style (8th edition)

  • Patel, Rishit. "Implementation of High Speed and Low Power Radix-4 8*8 Booth Multiplier in CMOS 32nm Technology ." Master's thesis, Wright State University, 2017. http://rave.ohiolink.edu/etdc/view?acc_num=wright1495371138748713

    Chicago Manual of Style (17th edition)

wright1495371138748713
2,154
© 2017, all rights reserved.
This open access ETD is published by Wright State University and OhioLINK.